ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |12-16 years| Pune)

Cisco; Pune District; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

Cisco is seeking an experienced Verification Engineer in Pune, India. The role involves designing and testing advanced pluggable and co-packaged optics, working with high-speed IPs and performing block-level verification.

The ideal candidate should have a Bachelor's or Master’s in Electronics Engineering and 12-16 years of functional verification experience, proficient in SystemVerilog, Python, C, and UVM methodology.

Key responsibilities include developing testbench components and analyzing coverage for complex functional verification scenarios.

Qualifications

• 12-16 years of functional verification experience.
• Strong skills in SystemVerilog, Python, C, and UVM methodology.
• Familiarity with UVM phases and CPU subsystems.

Responsibilities

• Develop testbench components for Silicon Photonics subsystems in a UVM-based framework.
• Build UVM components and implement verification strategies.
• Analyze coverage, debug functional simulations, and enhance coverage.

Skills

SystemVerilog

Python

C

UVM methodology

Digital design principles

Education

Bachelor’s or Master’s in Electronics Engineering

Tools

Synopsys

Cadence

Mentor Graphics

Job description

Meet the Team

Cisco’s Client Optics Group (COG) designs and delivers high‑speed optical transceivers and platforms that power Cisco's core data center networking solutions. We specialize in designing and integrating cutting‑edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry‑leading optical technologies within data centers with unprecedented speed, capacity, and reliability. Join us to shape COG’s groundbreaking optical solutions by designing, developing, and testing advanced pluggable and co‑packaged optics (CPO).

Your Impact

As a Verification Engineer, you will work with a diverse team of engineers spanning multiple disciplines. At the concept phase you will create verification documentation and work with senior engineers to define verification methodology and develop testbench components. During the initial design phase you will perform block‑level verification and later transition to full‑chip verification. You will run verification at block and chip level with high‑speed IPs such as ODSP, D2D IP, SerDes XSR, SerDes PAM4 integrated drivers/TIA, and control functions. You will develop functional coverage models, assertions, and debug complex verification issues within a UVM‑based framework. Prior to tapeout you will run functional scenarios with CPU firmware loaded and verify functionality at the CPU subsystem level. You may be involved in FPGA verification. Post‑silicon you will be involved in ATE test plan and test vector generation, ATE testing, and release to production.

Responsibilities

• Develop testbench components for Silicon Photonics subsystems in a UVM‑based framework.
• Build UVM components (agents, drivers, monitors, scoreboards, sequences) and implement constrained‑random and directed test strategies.
• Understand coverage metrics and functional specifications.
• Implement verification scenarios per full‑chip analog and digital verification test plans.
• Analyze coverage, add scenarios to enhance coverage, debug functional simulations, add corner verification cases, and resolve functional bugs.
• Code and verify firmware and C‑C, including automated analysis and reports using Python and C.
• Apply principles of RTL digital design and DFT (Design for Test).
• Maintain excellent organizational, teamwork, and communication skills.

Minimum Qualifications

• Bachelor’s or Master’s in Electronics Engineering (or equivalent/related).
• 12‑16 years of functional verification experience.
• Strong skills in SystemVerilog, Python, C, and UVM methodology.
• Familiarity with UVM phases, configuration mechanisms, factory overrides, and reuse across block, subsystem, and SoC‑level verification.
• Good understanding of CPU subsystems, FPGA, ODSP & integrated transceiver features, SerDes, Ethernet, D2D PHY IP & protocols.
• Experience with RTL design, simulation tools (Synopsys, Cadence, Mentor Graphics), and ASIC design flow.
• Team player, able to drive decisions quickly with consensus building.
• Strong analytical, problem‑solving, debugging, teamwork, communication, and organizational skills.