Senior Design Verification Engineer

Silicon Patterns; Bengaluru; On-site; INR 800,000 - 1,200,000; Full time

Job summary

A leading tech company is seeking a Senior Design Verification Engineer with over 5 years of experience in Ethernet IP/SoC verification. The candidate will develop and execute verification plans for high-speed Ethernet subsystems, utilizing their strong knowledge of SystemVerilog and UVM methodology. Key responsibilities include debugging design issues, contributing to automation improvements, and ensuring quality during verification. This role requires strong analytical and debugging skills, along with expertise in Ethernet protocols.

Qualifications

• 5+ years of experience in ASIC/SoC Design Verification.
• Strong hands-on experience with SystemVerilog and UVM methodology.
• Experience verifying Ethernet IPs and high-speed networking interfaces.

Responsibilities

• Develop verification plans and test environments for Ethernet subsystems.
• Execute simulations and debug failures to identify root causes.
• Track bugs and verification metrics to ensure tape-out quality.

Skills

SystemVerilog

UVM methodology

Functional verification

Ethernet protocols

Debugging skills

Education

Bachelor's or Master’s degree in Electronics/Electrical Engineering

Tools

VCS

Questa

Xcelium

Job description

Senior Design Verification Engineer – Ethernet

Experience: 5+ Years

Employment Type: Full-Time

Job Summary

We are looking for a highly skilled Senior Design Verification Engineer with strong experience in Ethernet IP/SoC verification. The candidate will work closely with architecture, RTL design, and system teams to develop and execute comprehensive verification strategies for high-speed Ethernet subsystems and networking IPs.

Key Responsibilities

• Understand architecture and RTL specifications of Ethernet IP/SoC components and develop verification strategies.
• Develop verification plans, test environments, and test cases for Ethernet subsystems and IP blocks.
• Build and maintain SystemVerilog/UVM based verification environments including testbench, drivers, monitors, checkers, and scoreboards.
• Execute simulations, regressions, and debug failures to identify root causes.
• Implement functional coverage, code coverage, and assertion-based verification methodologies.
• Work closely with RTL designers to debug and resolve design issues.
• Participate in SoC/IP level verification and bring-up activities.
• Contribute to verification automation, infrastructure improvements, and reusable verification components.
• Track bugs, coverage closure, and verification metrics to ensure tape-out quality.

Required Skills & Qualifications

• Bachelor’s or Master’s degree in Electronics/Electrical Engineering or related field.
• 5+ years of experience in ASIC/SoC Design Verification.
• Strong hands-on experience with:
• SystemVerilog and UVM methodology
• Functional verification and coverage-driven verification
• Assertion-based verification (SVA)
• Strong knowledge of Ethernet protocols and architecture (MAC, PHY, SerDes).
• Experience verifying Ethernet IPs, high-speed networking interfaces, or switching subsystems.
• Experience with simulation tools such as VCS, Questa, or Xcelium.
• Strong debugging and analytical skills.

Preferred Skills

• Experience with AXI/APB/AMBA protocols.
• Knowledge of PTP (IEEE 1588), RoCE, or high-speed Ethernet standards (100G/400G).
• Experience with emulation platforms or FPGA prototyping.
• Scripting experience in Python/Perl/TCL for verification automation.

Nice to Have

• Experience developing UVM environments from scratch.
• Exposure to networking stacks or data center networking architectures.
• Experience in post-silicon validation or system-level debugging.