DV - Ethernet

Proxelera; Bengaluru; On-site; INR 3,000,000 - 5,200,000; Full time

Job summary

Proxelera in Bengaluru is seeking an experienced ASIC verification engineer to own first-pass success across full development cycles. You will work hands-on with Verilog, SystemVerilog, UVM and C/C++, performing IP/sub-system and SoC verification.

You will architect DV infrastructure, collaborate with cross-functional teams, and contribute to data-center verification areas including RDMA, PCIe, Ethernet, and 400G MAC.

Qualifications

• Bachelor's degree in CS/CE or equivalent practical experience.
• 5+ years of relevant ASIC verification experience.
• Hands-on experience in Verilog, SystemVerilog, UVM, and C/C++.
• Experience in IP/sub-system and SoC verification using SystemVerilog UVM/OVM.
• Experience in RDMA, PCIe, SRIO, Ethernet, 400G Mac, RDMA, TSO, LRO, PSP, ROCE (RDMA over converged Ethernet).
• Experience with DV for data-center apps like Video, AI/ML and Networking.
• Experience architecting DV infra and executing the full verification cycle.
• DV at RTL and gate-level verification.
• Proficiency in Python, Perl, or TCL scripting for tools/flows.
• Analytical mindset to craft novel solutions for complex designs.
• Preferred collaboration with cross-functional teams.

Responsibilities

• Demonstrated experience with effective collaboration with cross functional teams.

Skills

Verilog

SystemVerilog

UVM

C/C++

Python

Scripting (Python, Perl, TCL)

Education

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

Job description

• Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• Track record of first-pass success in ASIC development cyclesAt least 5 years of relevant experience
• Hands-on experience in Verilog, SystemVerilog, UVM , C/C, Python based verification
• Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
• Experience in one or more of the following areas along with functional verification - RDMA, PCIe, SRIO & Ethernet, 400G Mac, RDMA, TSO, LRO, PSP,ROCE (RDMA over converged Ethernet), Congestion Control etc
• Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs
• Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
• Experience in IP, Cluster and SoC level verification in both RTL and Gate Level Setup
• Proficiency in scripting languages such as Python, Perl, or TCL to build tools and flows for verification environments
• Experience using analytical skills to craft novel solutions to tackle industry-level complex designs

Demonstrated experience with effective collaboration with cross functional teams Preferred