Engineering - Verification Engineer

Luxoft; Bengaluru; On-site; INR 1,200,000 - 2,100,000; Full time

Job summary

Luxoft is seeking talented design verification engineers for functional verification of x86 CPU cores in Bengaluru, India. You will create verification models, plans, and directed/random tests, collaborating with design teams to verify new CPU features across SOC, hardware, firmware, and software contexts.

You will debug failures, improve test benches, and apply scripting/AI tools to boost team productivity while ensuring comprehensive coverage and adherence to verification life cycle best

Qualifications

• 3-5 years ASIC design verification experience.
• Understanding or technical expertise in functional verification of microprocessor designs.
• Experience with Verilog/SystemVerilog HDL, programming in Perl/Python/Ruby, C/C++, Makefile and logic simulation.
• Experience with x86, ARM or any other industry standard microprocessor architecture.
• Strong understanding of computer architecture and assembly programming, preferably x86.
• A passion for computer architecture and a good understanding of modern out-of-order superscalar processor architecture.
• Strong understanding the design and verification life cycle.
• Experience in CPU cache/memory subsystem verification is a plus
• Simulation and debugging with a Verilog-based functional simulator.
• General functional verification experience with digital designs.
• Working experience in UNIX software environment.
• Strong problem-solving and debugging skills in both pre- and post-silicon environments.

Responsibilities

• Collaborate with design engineers and other verification engineers to understand new CPU features to be verified.
• Build test plan documentation, accounting for interactions with other features, various design sub-units within CPU, SOC and also hardware, firmware, and software use cases if applicable.
• Estimate time required to write new feature tests and any required changes to the test environment and tools.
• Develop directed and random verification tests.
• Understanding the existing test bench setup and look for opportunities to improve it.
• Debug test failures to determine the root cause; work with RTL design engineers to resolve design defects and correct any stimulus or testbench issues.
• Use scripting and internal AI tools to come up with innovative solutions to day-to-day problems and to improve individual as well as the team's productivity.
• Develop functional coverage properties as needed.
• Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements.
• Mentor junior engineers as needed.

Skills

ASIC verification

Verilog/SystemVerilog

Perl/Python/Ruby

C/C++

Makefile

x86/ARM architectures

UNIX

Debugging

Verification life cycle

Tools

Makefile

Verilog simulators

Python

Perl

Job description

Project description

We are looking for talented, detail-oriented, and motivated design verification engineers who are interested in functional verification of x86 microprocessor cores. You’ll have the unique opportunity to work on and learn about some of the industry’s cutting‑edge micro-architectural designs while you create verification models and plans for verifying the architecture of the X86 CPU core. Your contributions will impact products that span the global x86 market from server to desktop and laptop designs.

Responsibilities

• Collaborate with design engineers and other verification engineers to understand new CPU features to be verified.
• Build test plan documentation, accounting for interactions with other features, various design sub-units within CPU, SOC and also hardware, firmware, and software use cases if applicable.
• Estimate time required to write new feature tests and any required changes to the test environment and tools.
• Develop directed and random verification tests.
• Understanding the existing test bench setup and look for opportunities to improve it.
• Debug test failures to determine the root cause; work with RTL design engineers to resolve design defects and correct any stimulus or testbench issues.
• Use scripting and internal AI tools to come up with innovative solutions to day-to-day problems and to improve individual as well as the team's productivity.
• Develop functional coverage properties as needed.
• Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements.
• Mentor junior engineers as needed.

SKILLS

Must have

• ASIC design verification experience of 3-5 years.
• Understanding or technical expertise in functional verification of microprocessor designs.
• Experience with Verilog/System Verilog HDL, programming in Perl/Python/Ruby, C/C++, Makefile and logic simulation.
• Experience with x86, ARM or any other industry standard microprocessor architecture.
• Strong understanding of computer architecture and assembly programming, preferably x86.
• A passion for computer architecture and a good understanding of modern out-of-order superscalar processor architecture.
• Strong understanding the design and verification life cycle.
• Experience in CPU cache/memory subsystem verification is a plus
• Simulation and debugging with a Verilog-based functional simulator.
• General functional verification experience with digital designs.
• Working experience in UNIX software environment.
• Strong problem-solving and debugging skills in both pre- and post-silicon environments.

Nice to have

• Exposure to leadership or mentorship is an asset.
• Familiarity with use of AI is a plus.