Design Verification Engineer

Altera; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Altera is looking for a talented IP Verification Engineer to ensure the quality of IP blocks for complex SoCs. You will collaborate with teams to achieve silicon success, developing verification environments using SystemVerilog and UVM.

Qualifications include a degree in Electronics Engineering and 7+ years of relevant experience. Strong scripting skills in Python and expertise in verification methodologies are essential.

Qualifications

• 7+ years of experience in ASIC or FPGA design verification.
• Expertise in Hardware Description Languages (HDL) such as Verilog or VHDL.
• Strong experience in developing UVM-based testbenches.

Responsibilities

• Collaborate to define verification strategies and detailed test plans.
• Develop verification environments using SystemVerilog and UVM.
• Create and implement test cases to exercise design functionality.

Skills

SystemVerilog

UVM

Python

Verilog

Debugging skills

Education

Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, or related field

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

Job description

Job Description

We are seeking a talented and motivated IP Verification Engineer to join our team. In this role, you will be instrumental in ensuring the functional correctness and quality of our IP blocks for use in complex SoCs (System on a Chip). You will collaborate closely with architecture, design, and validation teams to achieve first-pass silicon success.

Key Responsibilities

• Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
• Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).
• Create and implement directed and random test cases and test sequences to exercise design functionality and uncover potential bugs.
• Develop verification components, including drivers, monitors, scoreboards, and checkers.
• Utilize SystemVerilog Assertions (SVA) and formal verification methods to enhance bug detection and verify complex properties.
• Execute simulation regressions, debug test failures, analyze root causes, and work with designers to implement corrective measures.
• Define and track functional and code coverage metrics to ensure verification completeness and drive coverage closure.
• Develop automation scripts and infrastructure using languages like Python or Perl to improve verification efficiency and flows.
• Participate in technical reviews of specifications, design documents, and test plans, providing valuable input and feedback.

Required Qualifications

• Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, or a related field.
• 7+ years of experience in ASIC or FPGA design verification.
• Expertise in Hardware Description Languages (HDL) like Verilog or VHDL and Hardware Verification Languages (HVL) such as SystemVerilog.
• Strong hands‑on experience in developing UVM-based testbenches and verification components.
• Proficiency in modern verification methodologies, including coverage‑driven verification (CDV) and assertion‑based verification (ABV).
• Familiarity with industry‑standard protocols such as AMBA (AXI, ACE, CHI, APB), PCIe, or Ethernet is a plus.
• Experience with simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).
• Strong scripting skills in Python, Perl, or Tcl for automation and data analysis.
• Excellent analytical, problem‑solving, and debugging skills.
• Strong communication skills and the ability to work effectively in a collaborative, cross‑functional team environment.

Job Type

Regular

Shift

Shift 1 (India)

Primary Location

Bengaluru, Karnataka, India

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.