CPU Design Verification (DV) Engineer

Veritis Group Inc; Bengaluru; On-site; INR 900,000 - 2,100,000; Full time

Job summary

Veritis Group Inc in Bengaluru, India is seeking an experienced CPU Design Verification Engineer to join our semiconductor team. The role focuses on CPU/IP verification, developing reusable UVM environments, and ensuring first-pass silicon success.

You will collaborate with design, architecture and validation teams to develop test cases, coverage plans, and debugging strategies using SystemVerilog and related tools to deliver high-quality silicon.

Qualifications

• 3-5+ years of Design Verification experience for CPU/SoC.
• Strong SystemVerilog and UVM knowledge.
• Experience in CPU/Processor verification.
• Understanding of computer architecture and processor pipelines.
• Experience with simulation and debugging tools (VCS, Xcelium, Questa).

Responsibilities

• Develop and execute verification plans for CPU/IP blocks.
• Design and implement reusable UVM-based verification environments.
• Develop test cases, assertions, scoreboards, and functional coverage.
• Perform debugging of simulation failures and root cause analysis.
• Collaborate with design, architecture, and validation teams to ensure first-pass silicon success.
• Track verification metrics, coverage closure, and bug resolution.

Skills

SystemVerilog

UVM

CPU/Processor verification

Computer architecture

Python/Perl/Shell

Education

Bachelor's or Master's degree in Electronics/ECE/Computer Engineering

Tools

VCS

Xcelium

Questa

Job description

We are looking for an experienced CPU Design Verification Engineer to join our semiconductor team in Bangalore. The ideal candidate should have strong expertise in CPU verification methodologies, SystemVerilog, and UVM with hands-on experience in verification of complex SoC/IP designs.

Key Responsibilities:

• Develop and execute verification plans for CPU/IP blocks.
• Design and implement reusable UVM-based verification environments.
• Develop test cases, assertions, scoreboards, and functional coverage.
• Perform debugging of simulation failures and root cause analysis.
• Collaborate with design, architecture, and validation teams to ensure first-pass silicon success.
• Track verification metrics, coverage closure, and bug resolution.

Required Skills:

• 3-5+ years of experience in Design Verification.
• Strong knowledge of SystemVerilog and UVM.
• Experience in CPU/Processor verification.
• Good understanding of computer architecture and processor pipelines.
• Experience with simulation and debugging tools (VCS, Xcelium, Questa, etc.).
• Knowledge of assertions (SVA), coverage-driven verification, and scripting (Python/Perl/Shell) is preferred.

Preferred Qualifications:

• Bachelor's or Master's degree in Electronics/ECE/Computer Engineering.
• Excellent debugging and problem-solving skills.
• Good communication and teamwork abilities.