Design-for-Test (DFT)

Cyient; Bengaluru; On-site; INR 900,000 - 1,200,000; Full time

Job summary

Cyient Bengaluru is seeking a seasoned DFT engineer to develop and implement DFT architecture for complex SoCs and IPs, collaborating with RTL and PD teams for robust signoff.

You will drive scan insertion, ATPG pattern generation, and DFT verification across RTL and gate levels, supporting silicon bring-up and post-silicon validation with a focus on PPA.

Responsibilities

• DFT implementation: develop and implement DFT architecture for complex SoCs/IPs; perform scan insertion using Cadence Modus DFT; define and implement full scan, scan compression, boundary scan (JTAG), MBIST/LBIST.

Tools

Cadence Modus DFT

Cadence Genus

Job description

Key Responsibilities

DFT Implementation

• Develop and implement DFT architecture for complex SoCs and IPs.
• Perform Scan Insertion using Cadence Modus DFT.
• Define and implement:
  • Full Scan
  • Scan Compression
  • Scan Chain Stitching
  • Test Point Insertion
  • Boundary Scan (JTAG)
  • MBIST Integration
  • LBIST (Preferred)

ATPG & Fault Coverage

• Generate ATPG patterns using Cadence Modus.
• Analyze and improve fault coverage.
• Debug pattern generation issues and coverage gaps.
• Perform diagnostics and failure analysis.

Synthesis & DFT Flow

• Execute synthesis using Cadence Genus.
• Work closely with RTL and Physical Design teams for DFT signoff.
• Support timing closure of DFT logic.
• Optimize DFT structures with minimal impact on PPA.

Verification & Validation

• Perform DFT verification at RTL and gate level.
• Validate scan chains and test modes.
• Run simulations for:
  • Scan Shift
  • Capture Mode
  • ATPG Pattern Validation
  • MBIST Verification

Silicon Bring-Up

• Support post-silicon validation and production testing.
• Analyze ATE test results and debug manufacturing failures.
• Collaborate with Product Engineering and Test Engineering teams.