DFT Manager

XQwave Pvt Ltd (Formerly Obsidian Solutions Pvt Ltd); Bengaluru; On-site; INR 1,200,000 - 2,200,000; Full time

Job summary

XQwave Pvt Ltd (Formerly Obsidian Solutions Pvt Ltd) is seeking a skilled DFT engineer in Bengaluru to define and implement DFT architectures for SoC/ASIC designs. You will lead scan insertion, chain stitching, and ATPG pattern validation, while supporting JTAG and boundary scan implementations.

The role includes MBIST/memory repair, DRC checks, GLS debugging, and ongoing test-coverage optimization. Collaboration with design, verification, and silicon validation teams is essential, with

Qualifications

• Develop DFT patterns for stuck-at, transition, bridge, and path delay faults.
• Verify MBIST/memory repair solutions.
• Perform DFT rule checks (DRC) and resolve violations.
• Support JTAG / boundary scan / IEEE 1149.1 implementation.
• Run and debug Gate Level Simulations (GLS) for DFT patterns.
• Analyze and improve test coverage, pattern count, and test time.
• Work with design, verification, physical design, and silicon validation teams.
• Support post-silicon bring-up and failure analysis.

Responsibilities

• Define and implement DFT architecture for SoC / ASIC designs
• Perform scan insertion and scan chain stitching
• Develop and validate ATPG patterns for stuck-at, transition, bridge, and path delay faults
• Implement and verify MBIST / memory repair solutions
• Perform DFT rule checks (DRC) and resolve violations
• Support JTAG / boundary scan / IEEE 1149.1 implementation
• Run and debug Gate Level Simulations (GLS) for DFT patterns
• Analyze and improve test coverage, pattern count, and test time
• Work closely with design, verification, physical design, and silicon validation teams
• Support post-silicon bring-up and failure analysis
• Create DFT documentation, methodology, and best-practice flows

Skills

DFT architecture

ATPG patterns

MBIST

JTAG/boundary scan

Gate Level Simulations

DFT checks

Job description

Define and implement DFT architecture for SoC / ASIC designs

Perform scan insertion and scan chain stitching

Develop and validate ATPG patterns for stuck-at, transition, bridge, and path delay faults

Implement and verify MBIST / memory repair solutions

Perform DFT rule checks (DRC) and resolve violations

Support JTAG / boundary scan / IEEE 1149.1 implementation

Run and debug Gate Level Simulations (GLS) for DFT patterns

Analyze and improve test coverage, pattern count, and test time

Work closely with design, verification, physical design, and silicon validation teams

Support post-silicon bring-up and failure analysis

• Create DFT documentation, methodology, and best-practice flows