DFT Lead

XQwave Pvt Ltd (Formerly Obsidian Solutions Pvt Ltd); Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

XQwave Pvt Ltd (Formerly Obsidian Solutions Pvt Ltd) is seeking a DFT engineer to define and implement DFT architecture for SoC/ASIC designs. The role involves scan insertion, scan chain stitching, and ATPG pattern development for various fault types.

You will also implement MBIST, conduct DRC checks, and support JTAG/boundary scan, with close collaboration across design, verification, PD, and silicon validation teams.

Qualifications

• DFT architecture design and implementation for SoC/ASIC
• Scan insertion and scan chain stitching
• Develop and validate ATPG patterns for stuck-at, transition, bridge, and path delay faults
• Implement and verify MBIST/memory repair solutions
• Perform DFT rule checks (DRC) and resolve violations
• Support JTAG/boundary scan/IEEE 1149.1 implementation

Responsibilities

• Run and debug Gate Level Simulations (GLS) for DFT patterns
• Analyze and improve test coverage, pattern count, and test time
• Work with design, verification, physical design and silicon validation teams
• Support post-silicon bring-up and failure analysis
• Create DFT documentation, methodology, and best-practice flows

Skills

DFT architecture

Scan insertion

ATPG patterns

MBIST / memory repair

DFT rule checks

JTAG / boundary scan

Gate Level Simulations

test coverage / test time

cross-functional collaboration

Tools

GLS

Job description

Define and implement DFT architecture for SoC / ASIC designs

Perform scan insertion and scan chain stitching

Develop and validate ATPG patterns for stuck-at, transition, bridge, and path delay faults

Implement and verify MBIST / memory repair solutions

Perform DFT rule checks (DRC) and resolve violations

Support JTAG / boundary scan / IEEE 1149.1 implementation

Run and debug Gate Level Simulations (GLS) for DFT patterns

Analyze and improve test coverage, pattern count, and test time

Work closely with design, verification, physical design, and silicon validation teams

Support post-silicon bring-up and failure analysis

Create DFT documentation, methodology, and best-practice flows