Design and Verification Engineer

Varite; Bengaluru; On-site; INR 2,000,000 - 3,500,000; Full time

Benefits offered by this job

Referral bonus program

Job summary

VARITE INDIA PRIVATE LIMITED is hiring a Design Verification Engineer in Bengaluru. The role focuses on SystemVerilog/UVM-based verification for SoC, subsystem, or IP designs, including constrained-random testing, SVA checks, and coverage closure. Collaboration with RTL, firmware and other teams is required for IP/SoC integration.

Minimum 5+ years of hands-on ASIC/SoC verification experience is expected. Proficiency in SystemVerilog, UVM, Python/Perl/Shell scripting, and familiarity with AMBA

Qualifications

• 5+ years of hands-on experience in ASIC/SoC Design Verification.
• Strong programming and verification experience using SystemVerilog.
• Strong hands-on experience with UVM methodology.
• Experience developing UVM-based testbenches and verification components.
• Hands-on experience with functional coverage and code coverage closure.
• Strong debugging skills using simulation logs and waveforms.
• Experience with SystemVerilog Assertions (SVA).
• Experience with AMBA protocols such as AXI, AHB and APB.
• Experience in SoC/subsystem-level verification.
• Experience with ARM or RISC-V based SoCs.
• Experience with C/C++ based firmware or software-driven verification.
• Scripting experience in Python, Perl or Shell.

Responsibilities

• Develop and maintain SystemVerilog/UVM-based verification environments for SoC, subsystem, or IP designs.
• Develop UVM components including sequences, sequencers, drivers, monitors, agents, scoreboards and reference models.
• Prepare verification plans, test strategies, test cases and verification scenarios based on design specifications.
• Execute constrained-random verification and directed testing for functional and corner-case scenarios.
• Develop and maintain SystemVerilog Assertions (SVA) for functional and protocol-level checks.
• Verify SoC interfaces and interconnects such as AMBA AXI, AHB and APB.
• Run simulation and regression suites and analyze failures to identify RTL, testbench or environment issues.
• Perform waveform-based debugging and root-cause analysis using industry-standard verification tools.
• Analyze functional and code coverage and drive coverage closure.
• Collaborate with RTL Design, Architecture, Firmware and other verification teams to resolve issues.
• Support verification at IP, subsystem and SoC integration levels.
• Develop reusable verification components and improve regression and verification infrastructure.
• Document verification results, bugs, coverage status and closure activities.

Job description

Job Title : Design Verification Engineer

Experience Required : 8 to 15 Year(s) - Immediate joiners

CTC Range : 20 to 35 LPA

Openings: 8+ years

Company Name: VARITE INDIA PRIVATE LIMITED

About The Client: A global IT services and consulting company, multinational information technology (IT), headquartered in Tokyo, Japan. The Client offers a wide array of IT services, including application development, infrastructure management, and business process outsourcing. Their consulting services span business and technology, while their digital solutions focus on transformation and user experience design. It excels in data and intelligence services, emphasizing analytics, AI, and machine learning. Additionally, their cybersecurity, cloud, and application services round out a comprehensive portfolio designed to meet the diverse needs of businesses worldwide.

About The Job:

Soc Verification Engineer

Essential Job Functions:

• Develop and maintain SystemVerilog/UVM-based verification environments for SoC, subsystem, or IP designs.
• Develop UVM components including sequences, sequencers, drivers, monitors, agents, scoreboards and reference models.
• Prepare verification plans, test strategies, test cases and verification scenarios based on design specifications.
• Execute constrained-random verification and directed testing for functional and corner-case scenarios.
• Develop and maintain SystemVerilog Assertions (SVA) for functional and protocol-level checks.
• Verify SoC interfaces and interconnects such as AMBA AXI, AHB and APB.
• Run simulation and regression suites and analyze failures to identify RTL, testbench or environment issues.
• Perform waveform-based debugging and root-cause analysis using industry-standard verification tools.
• Analyze functional and code coverage and drive coverage closure.
• Collaborate with RTL Design, Architecture, Firmware and other verification teams to resolve issues.
• Support verification at IP, subsystem and SoC integration levels.
• Develop reusable verification components and improve regression and verification infrastructure.
• Document verification results, bugs, coverage status and closure activities.

Qualifications:

• 5+ years of hands-on experience in ASIC/SoC Design Verification.
• Strong programming and verification experience using SystemVerilog.
• Strong hands-on experience with UVM methodology.
• Experience developing UVM-based testbenches and verification components.
• Hands-on experience with functional coverage and code coverage closure.
• Strong debugging skills using simulation logs and waveforms.
• Experience with SystemVerilog Assertions (SVA).
• Good understanding of RTL design and digital logic concepts.
• Experience with at least some AMBA protocols such as AXI, AHB and APB.
• Experience in SoC/subsystem-level verification.
• Experience with ARM or RISC-V based SoCs.
• Experience with C/C++ based firmware or software-driven verification.
• Scripting experience in Python, Perl or Shell.

Equal Opportunity Employer: VARITE is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. We do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity or expression, national origin, age, marital status, veteran status, or disability status.

Unlock Rewards: Refer Candidates and Earn.
If you're not available or interested in this opportunity, please pass this along to anyone in your network who might be a good fit and interested in our open positions. VARITE offers a Candidate Referral program, where you'll receive a one‑time referral bonus based on the following scale if the referred candidate completes a three-month assignment with VARITE.
Exp Req - Referral Bonus
0 - 2 Yrs. - INR 5,000
2 - 6 Yrs. - INR 7,500
6 + Yrs. - INR 10,000
About VARITE: VARITE is a global staffing and IT consulting company providing technical consulting and team augmentation services to Fortune 500 Companies in USA, UK, CANADA and INDIA. VARITE is currently a primary and direct vendor to the leading corporations in the verticals of Networking, Cloud Infrastructure, Hardware and Software, Digital Marketing and Media Solutions, Clinical Diagnostics, Utilities, Gaming and Entertainment, and Financial Services.