Design Verification Engineer

GiGa-Ops Global Solutions; Bengaluru; On-site; INR 1,000,000 - 2,000,000; Full time

Benefits offered by this job

Fast-paced engineering environment

Growth opportunities

Collaborative team culture

Job summary

A dynamic engineering firm in Bengaluru is seeking a Design Verification Engineer with expertise in SystemVerilog and UVM methodologies. The role involves developing formal verification plans, collaborating with design teams, and automating regression flows for the verification lifecycle from IP to silicon. Candidates must have 5 to 15 years of experience and a proven track record in RTL verification. Join a collaborative team focused on delivering high-quality, production-grade silicon while navigating challenging technical scenarios.

Qualifications

• 5 to 15 years of experience in design verification.
• Proven experience with SystemVerilog.
• Practical knowledge of UVM methodology.

Responsibilities

• Develop and execute formal verification plans.
• Collaborate with design teams for debugging.
• Automate regression flows and build verification infrastructure.

Skills

SystemVerilog

UVM testbench methodology

RTL verification

Scripting (Python/Tcl/Perl)

Assertion-based verification (SVA)

Tools

Synopsys VCS

Mentor Questa

Job description

1 week ago Be among the first 25 applicants

GiGa-Ops Global Solutions provided pay range

This range is provided by GiGa-Ops Global Solutions. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

Industry: Semiconductor / ASIC & SoC Design Verification — engineering team focused on verification of digital IP, blocks, and system‑on‑chip (SoC) integrations for embedded and telecom applications. This role is based in India and requires on‑site presence to collaborate closely with RTL designers, architects, and integration teams.

Primary Job Title: Design Verification Engineer (ASIC/SoC)

Experience: 5 to 15 Years

Only immediate joiners

Role & Responsibilities

• Develop and execute formal verification plans for digital blocks and SoC integrations using SystemVerilog and UVM methodologies.
• Implement directed and constrained‑random testbenches, stimulus generators, and assertions to validate RTL against specifications.
• Run simulations on industry simulators (VCS, Questa/Xcelium), analyze failures, debug RTL/testbench issues, and drive fixes with design teams.
• Measure and improve functional coverage; define coverage goals and close coverage holes using coverage‑driven strategies.
• Automate regression flows and build verification infrastructure using scripting (Python/Tcl/Perl) and CI tools to speed up turnaround.
• Collaborate with architecture, synthesis, timing, and validation teams to support silicon bring‑up, gate‑level verification, and signoff activities.

Skills & Qualifications

Must‑Have

• Proven experience with SystemVerilog for design verification
• Practical knowledge of UVM testbench methodology
• Experience with industry simulators (Synopsys VCS, Mentor Questa)
• Strong RTL verification skills (coverage‑driven, constraint‑random)
• Assertion‑based verification (SVA) experience
• Scripting for automation and debug (Python, Tcl, or Perl)

Preferred

• Experience with formal verification tools (e.g., JasperGold)
• Exposure to FPGA prototyping and emulation platforms (Palladium, Veloce)
• Low‑power verification knowledge (UPF) and gate‑level signoff experience

Benefits & Culture Highlights

• Hands‑on, fast‑paced engineering environment with clear ownership and growth paths.
• Opportunities to work on full verification lifecycle—from IP to SoC and silicon bring‑up.
• Collaborative on‑site team culture emphasizing technical excellence, mentorship, and measurable impact.

Location: Bangalore (On‑site). GiGa‑Ops Global Solutions is hiring experienced verification engineers who are passionate about building high‑quality, production‑grade silicon—if you thrive on deep technical challenges and delivering measurable verification outcomes, we encourage you to apply.

Skills: formal verification, soc, design verification, ip

Seniority level

• Mid‑Senior level

Employment type

• Full‑time

Job function

• Engineering and Information Technology

Industries

• Technology, Information and Internet

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