Lead STA Engineer

Broadcom Inc.; Pune District; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

Broadcom Inc. in Pune seeks an experienced STA Engineer to lead timing analysis across blocks and full chips, ensuring right-first-time silicon.

You will own timing constraints, perform setup/hold and variation-aware analyses, and drive ECO-based optimizations through tape-out with cross-functional teams. The role requires deep CMOS timing knowledge, proficiency with SDC and multi-path analyses, and hands-on experience with PrimeTime or Tempus.

Qualifications

• 15+ years of STA and timing closure experience for block/full-chip designs.
• Strong CMOS fundamentals, timing concepts and semiconductor design flow.
• Hands-on setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, MMMC.
• Good understanding of clock tree, clock uncertainty, latency, skew, and jitter.
• Expertise in timing constraints development and debugging.
• Strong knowledge of SDC, timing exceptions, false paths, multicycle paths, and case analysis.
• Experience with timing closure techniques and ECO methodologies.
• Hands-on experience with STA tools such as PrimeTime or Tempus.
• Scripting in Tcl, Perl, or Python; exposure to automation and flow development.
• Ability to analyze and resolve timing violations independently.
• Experience in low-power timing analysis and UPF/CPF-aware STA.
• Expertise with SI-aware timing, Crosstalk, and IR-drop-aware timing closure.
• Knowledge of advanced technology nodes and variation-aware signoff.
• Experience collaborating cross-functionally with PD, RTL, and Signoff.

Responsibilities

• Perform full-chip and block-level STA across all modes and corners.
• Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations.
• Work closely with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure.
• Develop and maintain timing constraints including SDC creation, validation, and signoff readiness.
• Drive timing closure through ECO implementation and timing optimization.
• Analyze timing impact due to process, voltage, and temperature variations.
• Support timing signoff for pre-layout and post-layout stages.
• Perform cross-functional reviews for timing convergence and provide recommendations.
• Generate timing reports and communicate closure status to project stakeholders.

Skills

STA expertise across block/full-chip

CMOS fundamentals and timing concepts

OCV/AOCV/POCV, derates, MMMC

Clock tree, skew, jitter understanding

SDC, false paths, multicycle paths, c.

ECO-based timing optimization

Synopsys PrimeTime, Cadence Tempus

Scripting: Tcl, Perl, Python

Automation and flow development

Independent timing violationresolution

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

Job Description

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet rigorous criteria for achieving Right-First-Time silicon. The STA Engineer is responsible for ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners. This role owns timing constraint development and validation, performs detailed setup/hold and variation-aware analysis, and partners closely with Synthesis, CTS, Physical Design, and Design teams to debug violations and drive ECO-based optimizations through tape out.

• Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners.
• Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations.
• Work closely with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure.
• Develop and maintain timing constraints including SDC creation, validation, and signoff readiness.
• Drive timing closure through ECO implementation and timing optimization.
• Analyze timing impact due to process, voltage, and temperature variations.
• Support timing signoff for pre-layout and post-layout stages.
• Perform cross-functional reviews for timing convergence and provide recommendations.
• Generate timing reports and communicate closure status to project stakeholders.

Minimum Qualifications

• 15+ years of experience in Static Timing Analysis (STA) and timing closure for block and/or full-chip designs.
• Strong understanding of CMOS fundamentals, timing concepts, and semiconductor design flow.
• Hands-on experience in setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts.
• Good understanding of clock tree, clock uncertainty, latency, skew, and jitter.
• Expertise in timing constraints development and debugging.
• Strong knowledge of SDC, timing exceptions, false paths, multicycle paths, and case analysis.
• Experience with timing closure techniques and ECO methodologies.
• Hands-on experience with industry-standard STA tools such as Synopsys PrimeTime or Cadence Tempus.
• Good scripting skills in Tcl, Perl, or Python. Exposure to automation and flow development.
• Ability to analyze and resolve timing violations independently.
• Experience in low-power timing analysis and UPF/CPF-aware STA.
• Expertise with SI-aware timing, Crosstalk analysis, and IR-drop-aware timing closure.
• Good knowledge of advanced technology nodes and variation-aware signoff methodologies.
• Experience in collaborating cross-functionally with PD, RTL, and Signoff teams.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Thank you for your interest in Broadcom! We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our video library and check out our Connected by Broadcom series. Follow us on Linked In Broadcom Inc.