Staff Engineer

Broadcom, Inc.; Karnataka; On-site; INR 1,500,000 - 2,600,000; Full time

Job summary

Broadcom, Inc. Central Engineering Group seeks a senior modeling engineer to lead memory model development for SRAM/RF/CAM/ROM memories used in ASIC-like flows. You will author, debug, and optimize models, drive improvements, and collaborate across design, compiler, and tool teams worldwide.

The role requires strong Verilog modeling, Linux proficiency, UVM test benches, and experience with DFT/ATPG/CAD tools. Flexibility to manage multiple projects is essential.

Qualifications

• BS in EE/CS/CE with 8+ years of industry experience or MS/PhD with related years as stated.
• Extensive Linux experience and command-line proficiency.
• Strong Verilog modeling skills and timing analysis knowledge.
• Experience with memory models (SRAM/RF/CAM/ROM) and DFT/CAD tools.
• Proficient with Verilog/RTL/Timing/Power modeling and UVM test benches.

Responsibilities

• Lead memory modeling and compiler development projects with design teams.
• Write model templates for integration into memory compilers for DFT/CAD tools.
• Collaborate with IP design, compiler teams and tool vendors globally.
• Respond to library support requests and address model issues across Broadcom.
• Document, prioritize tasks, and contribute to strategic objectives.

Skills

Verilog modeling

Linux

DFT/ATPG/Synthesizable model

Memory modeling

UVM

Scripting: Perl/Python/Tcl

Verilog/RTL/Timing/Power/CFG

Verilog/VCS/Questa/ModelSim

ASIC flows and CAD tools

Debugging and problem solving

Education

BS in EE/CS/CE

MS with 6+ years or PhD with 3+ years

Tools

VCS

Questa

ModelSim

ESPCV

Design Compiler

Genus

Job description

Broadcom's Central Engineering Group (CEG) is looking for an experienced, energetic and self-driven professional to join our team as a senior modeling engineer for the development and improvement of functional, timing, power, and DFT simulation models. This role will focus on authoring, debugging, and optimizing memory IP (SRAM, RF, CAM, ROM, etc.) EDA models used in ASIC-like design flows by chip teams throughout the company. This is a senior position with the expectation that the candidate can lead projects, proactively navigate complex technical issues, be able to work autonomously, and collaboratively participate in the establishment of strategic objectives. The candidate must have abilities to prioritize well, communicate clearly and concisely, deliver high quality solutions on-time, and possess excellent problem solving skills. This person will be expected to work across multiple facets of projects, have experience with ASIC development, and juggle multiple responsibilities at the same time exhibit excellent multitasking, context switching, and time management skills.

Responsibilities

• Lead memory modeling and compiler development projects working closely with design teams in an environment highly charged with technical complexities and dynamic schedule challenges.
• Be expected to demonstrate skills and abilities to lead and drive results & improvements, multitask and deliver high quality solutions in a timely fashion.
• Write model templates for integration into memory compilers to generate models used in DFT/CAD tools used in ASIC development flows.
• Participate in forums for model development, improvement and reviews, and will serve as a knowledge resource for peers, colleagues, and subordinates in the organization.
• Be expected to communicate well, document well, prioritize tasks and handle the multiple facets of model development projects independently to meet the business goals and commitments.
• Work to improve memory models and model generation flows for better performance, user experience and quality.
• Work directly with IP design teams, compiler teams and tool vendors globally to help resolve model related issues, and find timely solutions.
• Respond to library support requests and address tickets on model issues from product teams across Broadcom.

Qualifications

• The minimum engineering experience required is typically a BS degree in EE/CS/CE with programming/coding experience with 8+ years of industry experience, or an MS degree with 6+ or Ph.D. degree in EE/CS with 3+ years of industry experience.
• Have at least 3 years experience using Linux systems; possess excellent knowledge of Linux commands, file systems, and job execution.
• Strong preference for 5+ years of experience in Verilog modeling skills Static & Dynamic timing analysis knowledge.
• Experience with chip design tools and design flows, such as: DFT: Tessent, LogicVision, Modus, manufacturing test flows: at-speed scan test, Logic BIST, Memory BIST Synthesis: Design Compiler, Genus.
• Simulation: VCS, Questa, Verilog, waveform viewers, and simulation debug.
• UVM verification tetsbench and methodology development Conversant with Verilog/RTL/Behavioral/Timing/Power/DFT/ATPG/Synthesizable model development for SRAMs/RF/CAM/ROM, etc. memories.
• Experience in writing directed test bench in verilog for model verification.
• Knowledge and experience using simulators - NC, VCS, ModelSim, ESPCV is a must.
• Familiarity with memory model verification/QC flow is required.
• Scripting & flow automation, Perl, Python, Tcl, Shell programming skills are required.
• Able to work in agile and dynamic development environments.
• Excellent written and verbal communication skills.
• Skilled multi-tasking abilities and context switching skills are a must.
• Strong analytical, problem solving and quick learning skills are required.
• Good team player, methodical, eye for detail, independent, well organized, and have the ability to remain calm and composed in high pressure situations.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.

We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.