Associate III - VLSI SDC Design Engineer

UST; Dadri; On-site; INR 800,000 - 1,200,000; Full time

Job summary

UST is seeking a candidate with 3+ years of experience in standard cell design and verification in the VLSI domain. The role involves understanding different standard cells, performing verifications, benchmarking for performance, power, and area, and guiding junior team members in design and layout tasks.

Familiarity with digital flows would be advantageous. The ideal candidate will contribute to PPA benchmarking and work closely with peers to ensure robust standard cell implementations across

Qualifications

• Std cells experience with 3+ years in standard cell design and verification.
• Knowledge of various standard cells (combinational, sequential, level shifters).
• Ability to benchmark standard cells for PPA.
• Awareness of digital flow is a plus.

Responsibilities

• Lead and guide junior members in design and layout activities.
• Work on standard cell verification and related tasks.
• Collaborate on benchmarking and PPA optimization.

Skills

vlsi design

benchmarking

cell design

digiteal

Job description

Role Description

Job description: Std cells Person having 3+ years experience in standard cell design and verification. He / she should be having sound knowledge of different types of standard cells (Combinational, sequential Level shifters etc) and verifications of the same. He / She should be able to benchmark different standard cells for PPA. Awareness of digital flow will be a plus. Person is supposed to work with and guide other junior members in design and layout domain.

Skills

• vlsi design
• benchmarking
• cell design
• digiteal