VLSI PD Engineer

Source Konnect It Solutions; Hyderabad, Bengaluru; On-site; INR 800,000 - 1,200,000; Full time

Job summary

Source Konnect It Solutions in Hyderabad invites applications for a VLSI Physical Design role. The position focuses on transforming RTL to physical layout, using Fusion Compiler for synthesis, placement, routing, and floorplanning across advanced nodes such as 5nm and 3nm.

You'll handle signoff checks with Primetime, Star RC, Redhawk-SC, Calibre, and ECO implementations using Formality ECO and Prime Closure, contributing to robust silicon deliverables.

Responsibilities

• Physical Design: Provides services in transforming the RTL design into a physical layout of the chip using Synopsys Fusion Compiler synthesis and place-and-route tools. The physical design process involves specifying various constraints on the netlist, such as timing, power, area and design rules, and optimizing the layout for performance, quality, and reliability. We work on physical verification techniques such as Siemens Caliber DRC, LVS, antenna and density, especially in the latest nodes such as 5nm and 3nm.
• RTL to GDSII: Synthesis, Placement and Routing using Fusion Compiler; Block and SOC Floor planning using Fusion Compiler; Clock Tree Synthesis
• VLSI Physical Design
• Signoff checks: Timing using Primetime; Extraction using Star RC; EMIR closure using Redhawk-SC; Physical Verification using Calibre
• ¢ECO implementation: Logical ECOs using Formality ECO; Timing ECOs using Prime Closure

Job description

Skills

Job description

• Physical Design:
  • Provides services in transforming the RTL design into a physical layout of the chip using Synopsys Fusion Compiler synthesis and place-and-route tools. The physical design process involves specifying various constraints on the netlist, such as timing, power, area and design rules, and optimizing the layout for performance, quality, and reliability. We work on physical verification techniques such as Siemens Caliber DRC, LVS, antenna and density, especially in the latest nodes such as 5nm and 3nm.
• RTL to GDSII:
  • Synthesis, Placement and Routing using Fusion Compiler
  • Block and SOC Floor planning using Fusion Compiler
  • Clock Tree Synthesis
• VLSI Physical
• Design
• Signoff checks:
  • Timing using Primetime
  • Extraction using Star RC
  • EMIR closure using Redhawk-SC
  • Physical Verification using Calibre
• ¢ECO implementation:
  • Logical ECOs using Formality ECO
  • Timing ECOs using Prime Closure