Asic Verification Engineer

Acesoft Labs; Hyderabad; On-site; INR 1,500,000 - 2,300,000; Full time

Job summary

Acesoft Labs in Hyderabad, India, is seeking an experienced ASIC Verification Engineer to join a highly skilled team working on cutting-edge technology nodes. You will contribute to end-to-end IP/Block and Subsystem verification with SystemVerilog/UVM testbenches.

The role requires hands-on verification across AMBA protocols, RTL debugging, and building test plans, with collaboration across global teams to ensure first-pass silicon success.

Qualifications

• Expertise in IP/Block/Subsystem verification for ASIC projects.
• Strong understanding of AMBA protocols APB/AHB/AXI.
• Experience in building test plans and UVM environments.
• Proficient RTL debugging, scoreboards and assertions.
• Knowledge of Verilog and SystemVerilog is essential.
• Good written and verbal communication skills.
• Ability to work in cross-functional and globally dispersed teams.

Responsibilities

• Be part of a highly skilled ASIC team working on cutting-edge technology nodes.
• Responsible for end-to-end IP/Block and Subsystem-level verification from test plan creation to signoff.
• Develop SystemVerilog/UVM testbenches and ensure first-pass silicon success.
• Collaborate with domain experts across global locations to drive verification strategies.

Skills

IP/Block/Subsystem verification

AMBA protocols (APB/AHB/AXI)

UVM testbench development

RTL debugging

Verilog

SystemVerilog

Test plan development

Functional & code coverage

Assertions

Cross-functional collaboration

Communication skills

Job description

Job Title:

ASIC Verification Engineer

Experience Required:

5+ Years

Roles & Responsibilities:

• Be part of a highly skilled ASIC team working on cutting-edge technology nodes.
  
• Responsible for end-to-end IP/Block and Subsystem-level verification from test plan creation, SystemVerilog/UVM testbench development, to verification signoff.
  
• Ensure first-pass silicon success through comprehensive verification coverage, including mixed-mode verification.
  
• Collaborate with domain experts across global locations to drive technical initiatives and verification strategies.
  

Mandatory Skills Required:

• Expertise in IP/Block/Subsystem-level verification.
  
• Strong understanding of AMBA protocols: APB, AHB, AXI.
  
• Proven ability in building test plans, UVM environments, and testbenches.
  
• Proficient in RTL debugging, developing scoreboards, writing assertions, and implementing functional and code coverage.
  
• Solid knowledge of Verilog and SystemVerilog.
  
• Strong written and verbal communication skills.
  
• Ability to work effectively in cross-functional and globally dispersed teams.