RTL Front end verification, IP Verification Engineer

Acesoft Labs; Hyderabad; Hybrid; INR 1,200,000 - 2,500,000; Full time

Job summary

Acesoft Labs in Hyderabad, India is seeking an experienced ASIC verification engineer to contribute to latest technology nodes. You will design and implement test plans, build SystemVerilog/UVM environments, and verify IP blocks and subsystems.

Collaborate across globally dispersed teams, mentor juniors, ensure high-quality sign-off, and drive coverage strategies including AXI/AHB protocols and RTL debugging.

Qualifications

• Experience in IP/Block/Subsystem verification from test plan to sign-off.
• 3+ years of experience in ASIC verification.
• Strong knowledge of AXI/AHB protocols and AMBA interfaces.

Responsibilities

• Join a highly skilled ASIC team working on the newest technology nodes.
• Responsible for IP/Block and subsystem verification from test plan creation to sign-off.
• Ensure first pass product through multi-dimensional verification coverage.
• Mentoring and coaching junior team members.
• Pair with domain specialists across locations on core technical initiatives.

Skills

AXI/AHB protocols

IP/Block/Subsystem verification

SystemVerilog/UVM

RTL debugging

Education

M.S./M.Tech, BS/BE (Electronics)

Tools

UVM

Testbenches

Verilog

SystemVerilog

Job description

Roles & Responsibilities:

• To be part of a highly skilled ASIC Team working on the newest technology nodes
• Responsible for overall IP/Block and sub-system verification from test plan creation, SystemVerilog/ UVM testbench development to signoff
• Ensure first pass product through multi-dimensional verification coverage including mixed mode verification
• Mentoring and coaching junior team members
• Pair with similar domain specialists across other geographical locations on core technical initiatives

Skills required:

• Should have expertise in IP/Block/Subsystem level verification and AMBA protocols-APB/AHB/AXI.
• Proven track record of building test plan, UVM Environment and test benches
• Experience with RTL debugging, scoreboard, assertions, functional coverage coding and code coverage analysis
• Sound knowledge of Verilog and System Verilog languages
• The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.

Educational Qualification:

• M.S./M.Tech, BS/BE (Electronics)
• Experience Required : 3+ Years

Mandatory Skills:

• Should have working experience on AXI/AHB protocols.
• Should have working experience on IP/Block/Subsystem Verification starting from verification plan to sign off of the IP.
• Should be expert in System Verilog and UVM methodology.

Domain:

• IP/Block / Subsystem Verification (RTL Front end verification).