Principal Engineer, ASIC Design Verification

Ayar Labs; Bengaluru; On-site; INR 2,500,000 - 3,500,000; Full time

Job summary

Ayar Labs in Bengaluru is seeking a Principal Design Verification Engineer to lead the verification strategy for their next-generation silicon photonic chip. You will architect scalable verification environments while solving complex system-level challenges and mentoring a bright team of engineers.

The ideal candidate has an MS degree and over 12 years of experience in ASIC/SoC verification, with expert knowledge in SystemVerilog, UVM, and standard interface protocols. This role includes on-site work and flexible hours.

Qualifications

• 12+ years of relevant experience in ASIC/SoC verification.
• Expert-level proficiency in SystemVerilog and UVM.
• Proven track record of building verification environments from scratch.

Responsibilities

• Define and build modular, reusable, and scalable UVM testbench architectures.
• Set the standard for verification methodologies and coding guidelines.
• Collaborate with architects to define verification plans and ensure testability.

Skills

SystemVerilog

UVM

PCIe

ARM MCU

Python

Perl

Tcl

Shell scripting

Education

MS in Electrical Engineering, Computer Engineering, or related field

Tools

EDA tools

hardware emulation platforms

Job description

Location: Bengaluru, India

Job Id:597

# of Openings:0

Location: Bangalore (on-site, flexible hours)

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, farther, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD, and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale‑up architectures.

We are seeking a Principal Design Verification Engineer to lead the verification strategy for our next‑generation silicon photonic chip. In this role, you will serve as a technical lead, architecting scalable verification environments and driving high‑quality silicon from concept to tape‑out. You will look beyond block‑level testing to solve complex system‑level challenges, define methodologies, and mentor a growing team of bright engineers.

Essential Functions

• Architect Testbenches: Define and build modular, reusable, and scalable UVM testbench architectures for complex IP blocks and sub‑systems.
• Drive Methodology: Set the standard for verification methodologies, coding guidelines, and coverage metrics. Evaluate and deploy new EDA tools, formal verification techniques, or emulation flows.
• Strategic Planning: Collaborate with architects and RTL designers early in the cycle to define the verification plan, identify architectural bottlenecks, and ensure micro‑architecture testability.
• Complex Debugging: Lead the effort to debug elusive hardware bugs, root‑causing issues across RTL, firmware, and the verification environment.
• Technical Leadership: Mentor senior and junior engineers, conduct code reviews, and foster a culture of engineering excellence.
• Automation & Efficiency: Develop scripts and infrastructure to automate regression testing, performance analysis, and coverage closure.

Basic Qualifications

• MS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant experience in ASIC/SoC verification.
• Expert‑level proficiency in SystemVerilog and UVM (Universal Verification Methodology).
• Proven track record of building verification environments from scratch (agents, scoreboards, sequencers, etc.).
• Deep knowledge of standard interface protocols (PCIe, ARM MCU, AMBA/AXI, UCIe).
• Strong proficiency in scripting languages for automation (Python, Perl, Tcl, or Shell).
• Experience defining functional coverage groups and driving logic verification to 100% closure.

Preferred Qualifications

• Experience with formal property checking (VC Formal) and writing SVA (SystemVerilog Assertions).
• Hands‑on experience with hardware emulation platforms.
• Familiarity with RISC‑V or ARM architecture and coherency protocols.
• Experience in Analog/Mixed‑Signal (AMS) verification.
• Experience with C/C++ or SystemC modeling for reference models.
• Experience working on digital designs with multiple clock domains and clock dividers.
• Experience in verification of SerDes IP block interfaces in a complex SoC fabric environment.
• Experience in verification of the PCS, PMA SerDes layers and internal SerDes digital backends.
• Experience with verification of HBM memory interfaces (PHY and controller).
• Experience in formal model equivalence checking tools and verification methodology.
• Programming experience in Python.