ASIC Functional Design Verification Engineer

Pqangels Technologies; Bengaluru; On-site; INR 1,200,000 - 2,100,000; Full time

Benefits offered by this job

Onsite Opportunities

Fixed Pay

Health Insurance

Relocation Assistance

Job summary

PQAngels Technologies Pvt Ltd is seeking a Design Verification Engineer in Bengaluru. The role focuses on SystemVerilog/UVM for ASIC, subsystem and SoC verification, with responsibilities spanning verification environments, testbenches, and coverage closure.

The candidate should have 5–11 years of relevant experience and strong debugging skills, with exposure to high-speed interfaces and a collaborative, global team environment.

Qualifications

• 5–11 years of Design Verification experience.
• Strong SystemVerilog, UVM and SVA expertise required.
• Experience with ASIC/Subsystem/SoC verification and high-speed interfaces.

Responsibilities

• Develop verification plans and test strategies.
• Create reusable UVM-based verification environments.
• Develop and maintain SystemVerilog/UVM testbenches.
• Create test cases for Subsystem/SoC designs.
• Conduct functional coverage analysis and closure.
• Write SystemVerilog Assertions (SVA).
• Perform protocol and interface verification and debugging.
• Run simulations and regression tests.
• Support verification signoff and issue root cause analysis.
• Collaborate with Architecture, RTL, and physical design teams.

Skills

SystemVerilog

UVM

SVA

Functional Coverage

ASIC/SoC verification

High-speed interfaces

NoC

Python / TCL / PERL

ASIC/VLSI flow

Debugging/root-cause analysis

Regression testing

Education

Bachelor's or Master's in Electronics / Electrical / ECE / VLSI / Microelectronics

Tools

Synopsys VCS

Cadence Xcelium

Siemens QuestaSim

Synopsys Verdi

Job description

Design Verification Engineer

Company: PQAngels Technologies Pvt Ltd

Experience: 5 -11 Years

Locations: Bengaluru

Employment Type: Full-Time

About PQAngels Technologies

PQAngels Technologies is a product Engineering company built across the Silicon-to-Software stack. Founded by Experienced Engineers, we help customers accelerate innovation through Semiconductor, ASIC, VLSI, Embedded, and Product Engineering services.

Job Summary

We are looking for experienced Design Verification Engineers with strong expertise in SystemVerilog and UVM for ASIC, Subsystem and SoC verification.

The ideal candidate will be responsible for developing verification environments, creating test plans and testbenches, executing regressions, achieving functional coverage closure, debugging failures, and supporting verification signoff.

Key Responsibilities

• Develop detailed verification plans and test strategies.
• Design and develop reusable UVM-based verification environments.
• Develop and maintain SystemVerilog/UVM testbenches.
• Develop test cases and verification scenarios for Subsystem /SoC-level designs.
• Perform functional coverage analysis and coverage closure.
• Write and implement SystemVerilog Assertions (SVA).
• Perform protocol and interface verification.
• Execute simulations and regression tests.
• Debug RTL and verification issues and perform root cause analysis.
• Support verification signoff and closure activities.
• Ability to be an a independent contributor and collaborate with Architecture, RTL Design, Physical Design, and integration teams.
• Participate in design and verification reviews.
• Prepare verification documentation and reports.
• Participate in technical discussions and customer interactions when required.

Mandatory Technical Skills

• Strong experience in SystemVerilog
• Strong hands-on experience in UVM
• Experience with SystemVerilog Assertions (SVA)
• Strong understanding of Functional Coverage
• Hands-on experience in ASIC/Subsystem/SoC/ Functional Verification
• Experience with high-speed interfaces such as:
• PCIe
• DDR / DDR4 / DDR5/LPDDRX
• USB
• Ethernet
• NoC
• Strong debugging and root cause analysis skills
• Scripting experience in Python / TCL/PERL
• Good understanding of ASIC/VLSI Design and Verification flow

EDA Tools

• Synopsys VCS
• Cadence Xcelium
• Siemens QuestaSim
• Synopsys Verdi

Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, ECE, VLSI, Microelectronics, or a related field.
• 5-11 years of relevant experience in Design Verification.

Soft Skills

• Strong communication and interpersonal skills
• Excellent analytical and problem-solving abilities
• Strong stakeholder management skills
• Ability to work effectively in global teams
• Good ownership and collaboration skills
• Customer-focused approach

Why Join PQAngels Technologies?

• Opportunity to work on advanced semiconductor and ASIC projects
• Exposure to Subsystem, SoC, and end-to-end verification environments
• Opportunity to collaborate with experienced semiconductor engineers
• Exposure to global customers and challenging projects
• Strong learning and career growth opportunities

Benefits

• Onsite Opportunities
• Fixed Pay
• Health Insurance
• Relocation Assistance