ASIC Physical Design Engineer

Vhunt4u; Bengaluru; On-site; INR 1,000,000 - 2,000,000; Full time

Job summary

Vhunt4u is seeking an experienced engineer skilled in ASIC physical design to lead various implementation tasks. The role includes responsibilities such as full-chip implementation, clock tree synthesis, and scripting for design automation. Candidates should be able to mentor junior engineers while collaborating with cross-functional teams.

This position allows for remote work options, fostering flexibility in a highly technical environment.

Qualifications

• Expertise in ASIC physical design and full-chip implementation.
• Strong understanding of floor planning, methodology setup, and signoff processes.
• Experience in scripting for design flow automation using TCL, Python, or Perl.

Responsibilities

• Oversee SOC-level floor planning and partitioning.
• Provide technical mentorship to junior engineers.
• Collaborate with RTL, STA, and verification teams for design closure.

Skills

ASIC physical design

Full-chip implementation

Clock tree synthesis

Scripting (TCL, Python, Perl)

Problem-solving abilities

Tools

Synopsys Fusion Compiler

ICC2

Design Compiler

Job description

Job Role

• Expertise in ASIC physical design
• Expertise in full-chip implementation, bump placement, IP integration, and timing-driven PnR.
• Expertise in clock tree synthesis, power/clock gating, scan stitching, and design optimization.
• Expertise in floor planning, methodology setup, and signoff processes for large IPs.
• Expertise in scripting (TCL, Python, Perl) for design flow automation.
• Drive SOC-level floor planning, partitioning, and die size estimation.
• Manage hierarchical design flows, including block-level pin placement and HFNimplementation.
• Lead clock planning strategies at SOC and subsystem levels (Mesh/Tree).
• Provide technical mentorship to junior engineers and cross-functional teams.
• Own bump planning, including GPIO placement, pad ring generation, hard IP bump integration, and RDL routing.
• Strong communication and problem-solving abilities
• Collaborate with RTL, STA, and verification teams for design closure.
• Utilize multiple EDA tools like Synopsys Fusion Compiler, ICC2, Design Compiler

Remote Option

• May work from home