ASIC Physical Design Engineer

Vhunt4u; Ahmedabad District; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Vhunt4u in Ahmedabad District, Gujarat is looking for an expert in ASIC physical design. This role involves full-chip implementation, clock tree synthesis, and design optimization.

Candidates will be responsible for SOC-level floor planning, mentoring junior engineers, and collaborating across teams using EDA tools like Synopsys Fusion Compiler. Strong communication and problem-solving abilities are essential for this position.

Qualifications

• Expertise in full-chip implementation and timing-driven PnR.
• Experience with clock tree synthesis and power/clock gating.
• Strong background in floor planning and signoff processes.

Responsibilities

• Drive SOC-level floor planning and partitioning.
• Manage hierarchical design flows and provide technical mentorship.
• Collaborate with RTL, STA, and verification teams for design closure.

Skills

ASIC physical design

Scripting (TCL, Python, Perl)

Clock tree synthesis

Design optimization

Strong communication

Problem-solving

Tools

Synopsys Fusion Compiler

ICC2

Design Compiler

Job description

Description

• Expertise in ASIC physical design
• Expertise in full‑chip implementation, bump placement, IP integration, and timing‑driven PnR.
• Expertise in clock tree synthesis, power/clock gating, scan stitching, and design optimization.
• Expertise in floor planning, methodology setup, and signoff processes for large IPs.
• Expertise in scripting (TCL, Python, Perl) for design flow automation.
• Drive SOC‑level floor planning, partitioning, and die size estimation.
• Manage hierarchical design flows, including block‑level pin placement and HFN implementation.
• Lead clock planning strategies at SOC and subsystem levels (Mesh/Tree).
• Provide technical mentorship to junior engineers and cross‑functional teams.
• Own bump planning, including GPIO placement, pad ring generation, hard IP bump integration, and RDL routing.
• Strong communication and problem‑solving abilities.
• Collaborate with RTL, STA, and verification teams for design closure.
• Utilize multiple EDA tools like Synopsys Fusion Compiler, ICC2, Design Compiler.