ASIC Physical Design Engineer

Vhunt4u; Nagpur District; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Vhunt4u is looking for an expert in ASIC physical design based in Nagpur District, Maharashtra. The role involves full-chip implementation, bump placement, and managing hierarchical design flows while providing mentorship to junior engineers.

Candidates will drive SOC-level planning, work with various EDA tools, and collaborate with cross-functional teams. Remote work options are available for this position.

Qualifications

• Expertise in ASIC physical design and floor planning methodology.
• Strong skills in scripting for automation of design flows.
• Experience managing hierarchical design flows and providing mentorship.

Responsibilities

• Drive SOC-level floor planning and partitioning.
• Manage bump planning and die size estimation.
• Collaborate with RTL, STA, and verification teams.

Skills

ASIC physical design

Full-chip implementation

Timing-driven PnR

Scripting (TCL, Python, Perl)

Team collaboration

Problem-solving

Tools

Synopsys Fusion Compiler

ICC2

Design Compiler

Job description

Job Role

• Expertise in ASIC physical design
• Expertise in full-chip implementation, bump placement, IP integration, and timing-driven PnR.
• Expertise in clock tree synthesis, power/clock gating, scan stitching, and design optimization.
• Expertise in floor planning, methodology setup, and signoff processes for large IPs.
• Expertise in scripting (TCL, Python, Perl) for design flow automation.
• Drive SOC-level floor planning, partitioning, and die size estimation.
• Manage hierarchical design flows, including block-level pin placement and HFNimplementation.
• Lead clock planning strategies at SOC and subsystem levels (Mesh/Tree).
• Provide technical mentorship to junior engineers and cross-functional teams.
• Own bump planning, including GPIO placement, pad ring generation, hard IP bump integration, and RDL routing.
• Strong communication and problem-solving abilities
• Collaborate with RTL, STA, and verification teams for design closure.
• Utilize multiple EDA tools like Synopsys Fusion Compiler, ICC2, Design Compiler

Remote Option

• May work from home