ASIC Physical Design Engineer

Vhunt4u; Lucknow; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Vhunt4u is seeking an expert in ASIC physical design located in Lucknow, India. The role requires proficiency in full-chip implementation and timing-driven place and route. Ideal candidates will possess strong scripting skills in TCL, Python, or Perl, and have experience with SOC-level floor planning and partitioning.

The position involves mentoring junior engineers and collaborating with cross-functional teams. Strong communication and problem-solving abilities are essential. Join Vhunt4u to contribute your expertise in the cutting-edge field of ASIC design.

Qualifications

• Expertise in ASIC physical design.
• Expertise in full-chip implementation and timing-driven PnR.
• Strong communication and problem-solving abilities.

Responsibilities

• Drive SOC-level floor planning and partitioning.
• Provide technical mentorship to junior engineers.
• Collaborate with verification teams for design closure.

Skills

ASIC physical design

Full-chip implementation

Clock tree synthesis

Scripting (TCL, Python, Perl)

Communication

Problem-solving

Tools

Synopsys Fusion Compiler

ICC2

Design Compiler

Job description

Description :

• Expertise in ASIC physical design
• Expertise in full-chip implementation, bump placement, IP integration, and timing-driven PnR.
• Expertise in clock tree synthesis, power/clock gating, scan stitching, and design optimization.
• Expertise in floor planning, methodology setup, and signoff processes for large IPs.
• Expertise in scripting (TCL, Python, Perl) for design flow automation.
• Drive SOC-level floor planning, partitioning, and die size estimation.
• Manage hierarchical design flows, including block-level pin placement and HFN implementation.
• Lead clock planning strategies at SOC and subsystem levels (Mesh/Tree).
• Provide technical mentorship to junior engineers and cross-functional teams.
• Own bump planning, including GPIO placement, pad ring generation, hard IP bump integration, and RDL routing.
• Strong communication and problem‑solving abilities
• Collaborate with RTL, STA, and verification teams for design closure.
• Utilize multiple EDA tools like Synopsys Fusion Compiler, ICC2, Design Compiler