ASIC Physical Design Engineer

Vhunt4u; Chandigarh; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Vhunt4u, located in Chandigarh, India, is seeking an expert in ASIC physical design to drive SOC-level floor planning and work on chip implementation strategies. The role involves mentoring junior engineers and collaborating across various design teams to ensure effective design closure.

Ideal candidates will have a strong background in full-chip implementation, clock tree synthesis, and experience with EDA tools such as Synopsys Fusion Compiler and ICC2. Excellent communication and problem-solving skills are a must.

Qualifications

• Expertise in ASIC physical design.
• Ability in full-chip implementation and timing-driven PnR.
• Experience with scripting for design flow automation.

Responsibilities

• Drive SOC-level floor planning and partitioning.
• Lead clock planning strategies at SOC and subsystem levels.
• Provide technical mentorship to junior engineers.

Skills

ASIC physical design

Full-chip implementation

Clock tree synthesis

Scripting (TCL, Python, Perl)

Design optimization

Strong communication

Tools

Synopsys Fusion Compiler

ICC2

Design Compiler

Job description

Description :

• Expertise in ASIC physical design
• Expertise in full-chip implementation, bump placement, IP integration, and timing-driven PnR.
• Expertise in clock tree synthesis, power/clock gating, scan stitching, and design optimization.
• Expertise in floor planning, methodology setup, and signoff processes for large IPs.
• Expertise in scripting (TCL, Python, Perl) for design flow automation.
• Drive SOC-level floor planning, partitioning, and die size estimation.
• Manage hierarchical design flows, including block-level pin placement and HFN implementation.
• Lead clock planning strategies at SOC and subsystem levels (Mesh/Tree).
• Provide technical mentorship to junior engineers and cross-functional teams.
• Own bump planning, including GPIO placement, pad ring generation, hard IP bump integration, and RDL routing.
• Strong communication and problem‑solving abilities
• Collaborate with RTL, STA, and verification teams for design closure.
• Utilize multiple EDA tools like Synopsys Fusion Compiler, ICC2, Design Compiler