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Erbity is seeking a Physical Design Engineer to own the silicon journey from floorplan to signoff in Hyderabad. You will drive PnR/STA, target aggressive PPA goals and ensure robust signoff.
The role covers clock tree, routing optimization and extraction, with a strong emphasis on automation and end-to-end ASIC flow. Applicants should have hands-on experience with floorplanning, PnR, STA, EM/IR closure, and a proven track record in meeting tight targets.
This role is about owning the silicon journey from floorplan to signoff.
If PPA targets excite you more than scare you, this one's for you.