Work Mode: Hybrid
Experience: 6–8 Years
Employment Type: Full-time
Job Description
We are looking for an experienced Associate ASIC-FPGA Verification Engineer to join our engineering team in Bangalore. The ideal candidate will have strong hands‑on experience in digital functional verification, SystemVerilog, UVM, PCIe, and Ethernet MAC protocols.
Key Responsibilities
- Develop reusable verification components, including drivers, monitors, scoreboards, checkers, predictors, reference models, and coverage models using SystemVerilog and UVM.
- Perform digital functional verification of ASIC and FPGA designs at IP, subsystem, and system levels.
- Develop and maintain UVM‑based testbenches and Universal Verification Components (UVCs).
- Verify PCIe Gen4/Gen5/Gen6 and Ethernet MAC protocols.
- Develop test plans, test cases, assertions, and self‑checking reference models.
- Perform functional and code coverage analysis to achieve verification sign‑off.
- Debug simulation failures, analyze design issues, and work closely with RTL design and system engineering teams.
- Support regression testing and verification activities throughout the product development lifecycle, including tape‑out.
Mandatory Skills
- 6+ years of experience in digital functional verification for ASIC/FPGA.
- Strong hands‑on experience with SystemVerilog, Object‑Oriented Programming (OOP), and UVM.
- Hands‑on verification experience with PCIe Gen4/Gen5/Gen6, covering PHY, Link, and Transaction layers.
- Strong experience in Ethernet MAC protocol verification.
- Experience developing UVM testbench components for PCIe and Ethernet, including scoreboards, monitors, drivers, coverage models, and reference models.
- Experience with SystemVerilog Assertions (SVA), functional coverage, and code coverage.
- Experience with Linux/Unix environments and scripting using Python, Perl, Shell, or Make.
- Experience with version control tools such as Git, SVN, or CVS.
- Verification experience on at least one ASIC/FPGA product through the tape‑out lifecycle.
Preferred Skills
- Experience with power‑aware simulation and gate‑level simulation debugging.
- Knowledge of avionics protocols and DO‑254 standards.
- Experience in IP, subsystem, and SoC‑level verification.
Education
- Bachelor's or Master's degree in Electronics, Electrical Engineering, or a related field.
- A Master's degree in Microelectronics, VLSI, CAD, or Embedded Systems is an advantage.