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VeriFast Technologies, a product engineering and semiconductor partner, seeks a Senior Design Verification Engineer for an on-site role in Ahmedabad. You will lead verification planning and testbench architecture, ensuring functional correctness of ASIC/SoC designs, while driving coverage and methodology improvements.
You will mentor junior engineers, collaborate with RTL/design/software teams, and adopt AI-driven verification flows where applicable.
VeriFast Technologies is a product engineering and semiconductor technology partner delivering chip-to-cloud solutions across ASIC/SoC, design verification, embedded systems, edge AI, IoT, software, and quality engineering. The company combines deep engineering expertise with AI-driven innovation to accelerate product development and digital transformation for global customers. Its core capabilities span AI-powered design verification through the VeriQuest platform, end-to-end silicon engineering and ASIC solutions from RTL to GDSII, and advanced embedded, edge AI, and IoT development. VeriFast also focuses on AI-driven quality engineering for predictive defect mitigation and intelligent software and AI solutions that enable scalable, connected products.
The Senior Design Verification Engineer role is a full-time, on-site position based in Ahmedabad. The individual in this role will lead verification planning, testbench architecture, and execution for complex ASIC/SoC designs, ensuring functional correctness and high-quality silicon. Day-to-day responsibilities include developing and reviewing verification strategies, creating and maintaining testbenches, writing and executing test cases, analyzing coverage, and driving closure on verification metrics. The role involves debugging functional issues, collaborating with RTL design, architecture, and software teams, and contributing to methodology improvements and automation initiatives. The Senior Engineer will also mentor junior team members, support integration and regression activities, and help adopt AI-driven verification tools and flows where applicable.