Synthesis Engineer

Mirafra; Hyderabad, Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Mirafra is hiring Synthesis Engineers with 2 to 6 years of experience for our VLSI team. The role focuses on RTL Synthesis, DC/FC, timing concepts, and RTL-to-GDSII flow. Location options include Hyderabad and Bangalore, with an immediate to short notice period.

The team emphasizes hands-on work and problem-solving in a dynamic environment. We seek engineers proficient in Verilog/SystemVerilog, scripting (Tcl/Perl/Python), and optimization of timing, area, and power.

Qualifications

• Hands-on RTL synthesis experience with design implementation.
• Strong knowledge of DC/FC tools for optimization.
• Experience with SDC timing constraints and timing analysis.
• Proficient in RTL-to-GDSII flow and place-and-route concepts.
• Verilog/SystemVerilog coding and testbench skills.
• Proficient scripting in Tcl/Perl/Python for automation.
• Ability to debug and solve synthesis issues efficiently.
• Experience in timing, area, and power optimization.

Skills

RTL Synthesis

Synopsys DC/FC

SDC constraints & timing

Timing, area & power

Verilog/SystemVerilog

Tcl/Perl/Python scripting

RTL-to-GDSII flow

Debugging & problem-solving

Job description

Hi,

We are hiring Synthesis Engineers with 2 to 6 years of experience for our VLSI team.

Role: Synthesis Engineer
Experience: 26 Years
Location: Bangalore & Hyderabad
Notice Period: Immediate to 30 Days preferred

Key Skills:

• Hands-on experience in RTL Synthesis
• Strong knowledge of Synopsys Design Compiler (DC) / Fusion Compiler (FC)
• Good understanding of SDC constraints and timing concepts
• Experience in timing, area and power optimization
• Good knowledge of Verilog/SystemVerilog
• Experience with Tcl/Perl/Python scripting
• Understanding of RTL-to-GDSII flow
• Good debugging and problem-solving skills