ASIC Electrical Analysis and Convergence Engineer, Silicon Engineering

Google; Bengaluru; Sur place; INR 1 500 000 - 2 500 000; Plein temps

Résumé du poste

Google is seeking a PDN convergence engineer to join our hardware Platforms and Devices team. You will own block or subsystem signoff for complex logic and collaborate with Physical Design to ensure silicon meets functional and PPA requirements.

You will drive PG bump assignments, IR/EM convergence, and ESD for Google IPs, write scripts to accelerate convergence, and mentor junior engineers. This role blends cutting-edge design with hands-on tool usage and cross-functional teamwork across

Qualifications

• Bachelor's degree in an engineering or related field, or equivalent practical experience.
• 4 years of experience in PDN convergence (IP/SOC) or related PDN work.
• Experience with CAD/EDA tool support or PDN methodology.

Responsabilités

• Drive PG bump assignments, RDL routing, IR/EM, and Inrush convergence for multiple IPs.
• Lead ESD convergence for Google IPs using DEF-based tools.
• Suggest improvements for PG Grid, flows, and PDN methodologies, and coordinate with CAD/EDA partners.
• Write moderate complexity scripts to accelerate convergence and analyze results.
• Mentor junior engineers and interns to achieve convergence across IPs.

Connaissances

PDN convergence experience

IP/SOC PDN

CAD/EDA tool support

PDN methodology

Formation

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science

Outils

EDA tools

CAD tools

PDN design tools

Description du poste

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience in Power Delivery Network(PDN) convergence (IP/SOC level), CAD/EDA tool support, or PDN methodology.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with Power Grid design, PG bump assignment, and RDL optimizations.
• Experience with IR (Static, Dynamic), EM (Power/Signal), ESD, Inrush, and PDN convergence for moderate-to-high complexity IPs.
• Understanding of IR methodology and EDA tools.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Be a part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-customer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency and integration.

In this role, you will own block or subsystem signoff for complex logic blocks and work closely with Physical Design (PD) collaterals in IR/Electromigration (EM) to ensure high-quality silicon meets functional, manufacturing, and PPA requirements for subsystems.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Drive PG (Power and Ground) bump assignments, Redistribution Layer (RDL) routing, IR (Static, Dynamic), EM and Inrush convergence for multiple IPs using industry-standard analysis tools (RedHawk-SC, Voltus, SPICE, etc.).
• Lead Electrostatic Discharge (ESD) convergence for low-to-mid complexity Google IPs utilizing basic ESD concepts and DEF-based tools (Pathfinder-Classic, Pathfinder-SC, etc.).
• Suggest basic to moderate complexity changes for PG Grid, flows, and methodologies. Partner with internal experts, technology teams, CAD, and EDA partners to address tool enhancements, bugs, and workarounds.
• Write moderate complexity code/scripts to accelerate convergence, streamline debug, and perform deep-dive analysis.
• Guide junior engineers and interns to achieve convergence across multiple IPs and methodology initiatives.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .