ASIC Electrical Analysis and Convergence Engineer, Silicon Engineering

Google LLC; Bengaluru; Presencial; INR 1 400 000 - 2 100 000; Tempo integral

Resumo da oferta

Google LLC is seeking an ASIC Electrical Analysis and Convergence Engineer in Silicon Engineering to own signoff for complex logic blocks. You will collaborate with PD collaterals in IR/EM to ensure silicon meets functional, manufacturing, and PPA targets across subsystems.

You will drive PG bump assignments, RDL routing, and convergence for multiple IPs, while mentoring juniors and collaborating with CAD/EDA partners. Strong scripting skills and industry tool experience are valued.

Qualificações

• Bachelor's degree or equivalent practical experience.
• 4 years of PDN convergence, CAD/EDA tool support, or PDN methodology.

Responsabilidades

• Own signoff for complex logic blocks with IR/EM collaboration.
• Drive PG bump assignments, RDL routing, IR/EM convergence.
• Lead ESD convergence for Google IPs using DEF-based tools.
• Write scripts to accelerate convergence and debugging.
• Mentor junior engineers and interns.

Conhecimentos

PDN convergence

CAD/EDA tool support

IR methodology

EDU tools

Power Grid design

RDL optimizations

ESD convergence

EM (Power/Signal)

Inrush convergence

Scripting

Mentoring juniors

Formação académica

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with emphasis on computer architecture

Ferramentas

RedHawk-SC

Voltus

SPICE

Pathfinder-Classic

Pathfinder-SC

Descrição da oferta de emprego

ASIC Electrical Analysis and Convergence Engineer, Silicon Engineering

Share ASIC Electrical Analysis and Convergence Engineer, Silicon Engineering

X In most instances, this position requires in-person interviews as part of the hiring process.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 4 years of experience in Power Delivery Network(PDN) convergence (IP/SOC level), CAD/EDA tool support, or PDN methodology.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with Power Grid design, PG bump assignment, and RDL optimizations.
  
• Experience with IR (Static, Dynamic), EM (Power/Signal), ESD, Inrush, and PDN convergence for moderate-to-high complexity IPs.
  
• Understanding of IR methodology and EDA tools.
  

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Be a part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-customer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency and integration.

In this role, you will own block or subsystem signoff for complex logic blocks and work closely with Physical Design (PD) collaterals in IR/Electromigration (EM) to ensure high-quality silicon meets functional, manufacturing, and PPA requirements for subsystems.
The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Drive PG (Power and Ground) bump assignments, Redistribution Layer (RDL) routing, IR (Static, Dynamic), EM and Inrush convergence for multiple IPs using industry-standard analysis tools (RedHawk-SC, Voltus, SPICE, etc.).
• Lead Electrostatic Discharge (ESD) convergence for low-to-mid complexity Google IPs utilizing basic ESD concepts and DEF-based tools (Pathfinder-Classic, Pathfinder-SC, etc.).
• Suggest basic to moderate complexity changes for PG Grid, flows, and methodologies. Partner with internal experts, technology teams, CAD, and EDA partners to address tool enhancements, bugs, and workarounds.
• Write moderate complexity code/scripts to accelerate convergence, streamline debug, and perform deep-dive analysis.
• Guide junior engineers and interns to achieve convergence across multiple IPs and methodology initiatives.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.