ASIC Electrical Analysis and Convergence Engineer

Google India Pvt Ltd; Bengaluru; On-site; INR 3,000,000 - 4,500,000; Full time

Job summary

Google India Pvt Ltd in Bengaluru seeks a mid-level PDN engineer to own block or subsystem convergence for complex logic blocks. You will collaborate with PD, EM, and EDA teams to ensure high-quality silicon that meets performance and manufacturing targets.

The role involves leading convergence efforts for multiple IPs, writing scripts to speed up analysis, and mentoring juniors to advance PDN methodologies across projects.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field or equivalent practical experience.
• 4 years of experience in PDN convergence (IP/SOC level), CAD/EDA tool support, or PDN methodology.

Responsibilities

• Drive PG bump assignments, RDL routing, IR/EM and Inrush convergence for multiple IPs using industry-standard tools.
• Lead ESD convergence for low-to-mid complexity Google IPs using DEF-based tools.
• Suggest basic to moderate changes for PG Grid, flows, and methodologies.
• Partner with internal experts, CAD, and EDA teams to address tool enhancements and bugs.
• Write moderate complexity scripts to accelerate convergence and perform deep-dive analysis.
• Guide junior engineers and interns to achieve convergence across multiple IPs and methodologies.

Skills

PDN convergence

CAD/EDA tool support

PDN methodology

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

Minimum qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience in Power Delivery Network(PDN) convergence (IP/SOC level), CAD/EDA tool support, or PDN methodology.

Preferred qualifications

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with Power Grid design, PG bump assignment, and RDL optimizations. Experience with IR (Static, Dynamic), EM (Power/Signal), ESD, Inrush, and PDN convergence for moderate-to-high complexity IPs. Understanding of IR methodology and EDA tools.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Be a part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-customer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency and integration. In this role, you will own block or subsystem signoff for complex logic blocks and work closely with Physical Design (PD) collaterals in IR/Electromigration (EM) to ensure high-quality silicon meets functional, manufacturing, and PPA requirements for subsystems. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Be a part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-customer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will own block or subsystem signoff for complex logic blocks and work closely with Physical Design (PD) collaterals in IR/Electromigration (EM) to ensure high-quality silicon meets functional, manufacturing, and PPA requirements for subsystems.

Responsibilities

• Drive PG (Power and Ground) bump assignments, Redistribution Layer (RDL) routing, IR (Static, Dynamic), EM and Inrush convergence for multiple IPs using industry-standard analysis tools (RedHawk-SC, Voltus, SPICE, etc.).
• Lead Electrostatic Discharge (ESD) convergence for low-to-mid complexity Google IPs utilizing basic ESD concepts and DEF-based tools (Pathfinder-Classic, Pathfinder-SC, etc.).
• Suggest basic to moderate complexity changes for PG Grid, flows, and methodologies.
• Partner with internal experts, technology teams, CAD, and EDA partners to address tool enhancements, bugs, and workarounds.
• Write moderate complexity code/scripts to accelerate convergence, streamline debug, and perform deep-dive analysis.
• Guide junior engineers and interns to achieve convergence across multiple IPs and methodology initiatives.

Experience Level

Mid Level