System on Chip (SoC) Constraints Design Engineer

Google India Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 6,800,000; Full time

Benefits offered by this job

Health insurance

Employee stock options

Job summary

Google India Pvt Ltd in Bengaluru is seeking a mid-level hardware design engineer to drive timing constraints and sign-off for custom silicon projects powering Pixel and other devices.

You will partner with RTL teams, develop and validate SDC flows, and ensure robust clocking and CDC strategies across corners and modes. This role offers exposure to cutting-edge EDA tools and close collaboration with Google Silicon teams.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering, CS, or related field, or equivalent practical experience.
• 4 years of experience with digital logic design principles and RTL design concepts.
• 1 year of experience with Static Timing Analysis, constraints development/validation, sign-off corner definitions, process margining, and timing goals with PDK changes.
• Experience with scripting languages (Python, Perl, Tcl) to automate workflows and parse EDA reports.

Responsibilities

• Collaborate with Architecture/RTL teams to capture timing intent and drive timing convergence.
• Lead development/validation of Synopsys Design Constraints (SDC) for SoC subsystems and top-level integration.
• Understand clocking structures and CDC strategies to ensure robust timing across modes.
• Coordinate with design teams for sign-off timing convergence and constraints promotion.

Skills

Digital logic design

RTL design concepts

Scripting (Python, Perl, Tcl)

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Synopsys Design Constraints (SDC)

Job description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with digital logic design principles, RTL design concepts.
• 1 year of experience with Static Timing Analysis, Constraints development and its validation, sign-off corner definitions, process margining, and setup of frequency goals with technology scaling and Process Design Kit (PDK) changes.
• Experience with scripting languages (e.g., Python, Perl, Tcl) to automate workflows, parse electronic design automation (EDA) reports, and develop custom utilities.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience in developing constraints and validating the same using Timing Constraints Manager (e.g., Synopsys)/TimeVision (e.g., Ausdia).
• Experience with liberty timing models and Static Timing Analysis tools (e.g., TCM/TimeVision, Primetime, Tempus).
• Understanding of SoC Architecture, memory hierarchy, coherency, fabric interconnect protocols, clocking, and power management.
• Understanding of various external Input/Output (IO) protocols.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google Silicon is developing custom silicon solutions that power the future of Google's direct-to-consumer products, including Pixel and other devices. We combine the best of Google's Artificial Intelligence (AI), Software, and Hardware to create radically helpful experiences. In this role, you will be part of a team that pushes boundaries, shaping the next generation of hardware experiences by delivering unparalleled power, performance, area efficiency, and integration. You will be part of Google's Silicon team, developing hardware and software to enable Google's continuous innovations in working with Application Specific Integrated Circuits (ASIC). You will drive the complete design constraints development, its validation, working on sign-off timing convergence for designs including deciding the initial timing goals, setting up the timing analysis flows and methodology, and working with the implementation engineers to hit the timing goals. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Google Silicon is developing custom silicon solutions that power the future of Google's direct-to-consumer products, including Pixel and other devices. We combine the best of Google's Artificial Intelligence (AI), Software, and Hardware to create radically helpful experiences. In this role, you will be part of a team that pushes boundaries, shaping the next generation of hardware experiences by delivering unparalleled power, performance, area efficiency, and integration. You will be part of Google's Silicon team, developing hardware and software to enable Google's continuous innovations in working with Application Specific Integrated Circuits (ASIC). You will drive the complete design constraints development, its validation, working on sign-off timing convergence for designs including deciding the initial timing goals, setting up the timing analysis flows and methodology, and working with the implementation engineers to hit the timing goals.

Responsibilities

Collaborate with Architecture/Microarchitecture/ Register-Transfer Level (RTL) design teams to capture timing intent, and drive timing convergence. Lead the development and validation of Synopsys Design Constraints (SDC) for complex System on a Chip (SoC) subsystems and top-level integration from architecture/microarchitecture documents that gets used in static timing analysis as well as physical design implementation. Understand clocking structures and Clock Domain Crossing (CDC) strategies to ensure robust timing across all functional and test modes. Design constraints validation across multiple corners/modes using Fishtail/Timevision. Work closely with the design team and block owners throughout the project for sign-off timing convergence. Constraints promotion and demotion flow using fishtail, timevision.

Experience Level

Mid Level