ASIC Design Verification Engineer

Ceremorphic, Inc.; Hyderabad; On-site; INR 4,200,000 - 7,000,000; Full time

Job summary

Ceremorphic, Inc. is seeking verification engineers to work on high-performance microprocessors and ML accelerators.

You will develop UVM-based test environments, create and sign off assertions, and drive coverage closures across block-, sub-system-, and chip-level verification. The role requires scripting in Perl, Python, and Tcl to automate flows, plus deep knowledge of AHB/AXI SoCs, ARM M-series or RISC-V architectures, and verification of USB, PCIe, Ethernet, and DDR interfaces.

Qualifications

• Experience in UVM-based test environment development.
• Experience in creation and signoff of assertions and constrained random generation.
• Automation using Perl, Python, and Tcl for verification flows.
• Knowledge of AHB/AXI SoC architectures.
• Strong knowledge of ARM M-series or A-Series MCU, and RISC-V.
• Exposure to USB, PCIe, Ethernet, and DDR interfaces.

Responsibilities

• Lead verification teams for logic validation, emulation, and pre/post-silicon validation.
• Possess proven experience in delivering high-quality products to market.

Skills

UVM testbench

Assertions signoff

Constrained random

Functional coverage

Code coverage

Perl

Python

Tcl

AHB/AXI

ARM M-series

RISC-V

USB interfaces

PCIe interfaces

Ethernet

Mobile DDR

Quad/Octa-SPI

Low power verification

Chip-level verification

Block/sub-system verification

Job description

Looking for candidates to work on verification of high performance and low power Microprocessor / Machine Leaning Processor / Logic Design

Key Requirements

• Expertise in UVM based test environment development.
• Experience in creation and signoff of assertions, constrained random generation, functional and code coverage.
• Expertise in scripting languages like Perl, Python, Tcl to achieve automation of verification methodologies and flows.
• Expertise in AHB/AXI based SoC Architectures.
• Strong knowledge in ARM M-series or A-Series MCU, RISC-V architectures.
• Experience in verifying high-speed interfaces like USB, PCIe 4x/5x, Ethernet, Mobile DDR, Quad/Octa-SPI.
• Knowledge in low power verification.
• Hands-on experience in developing block-level, sub-system level and chip-level verification environments from “scratch”.
• Senior positions require leading verification teams to drive both logic validation, emulation, pre- and post-silicon validation.
• Management positions require proven experience of leading teams and delivering high quality products to market.