AMS Verification Engineer / Lead

Mount Talent Consulting Pvt Ltd.; Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Mount Talent Consulting Pvt Ltd is seeking an experienced AMS Verification Engineer in Bengaluru to verify analog and mixed-signal IPs, develop testbenches, and ensure functional correctness through simulation and coverage closure.

You will build SystemVerilog/UVM verification environments, develop RNM models for analog blocks, verify interactions with digital design, and drive regression and sign-off in collaboration with SoC verification teams.

Qualifications

• Experience in AMS verification of analog/mixed-signal IPs.
• Strong knowledge of SystemVerilog and UVM.
• Experience with Real Number Modeling (RNM).
• Familiarity with analog blocks (ADCs, DACs, PLLs, oscillators, LDOs).
• Experience with functional coverage, debugging, and regression management.
• AMS simulation tools and verification flows.

Responsibilities

• End-to-end verification of analog and mixed-signal IPs.
• Develop verification plans and testbenches for AMS designs.
• Build SystemVerilog/UVM based verification environments.
• Develop and verify RNM for analog blocks.
• Verify interactions between analog and digital components.
• Perform coverage analysis and drive regression closure.
• Collaborate with analog, digital, and SoC verification teams.
• Manage verification schedules and deliverables.
• Support regression execution and sign-off.

Skills

AMS verification

SystemVerilog

UVM

RNM

Analog IPs

AMS tools

Tools

Cadence Virtuoso

Job description

We are looking for an experienced AMS Verification Engineer with strong expertise in analog and mixed-signal verification, SystemVerilog, UVM, and real-number modeling (RNM). The candidate will responsible for verification activities for mixed-signal IPs and ensure functional correctness through simulation, testbench development, and coverage closure.

Key Responsibilities

• End-to-end verification of analog and mixed-signal IPs.
• Develop verification plans, test strategies, and testbenches for AMS designs.
• Build and maintain SystemVerilog/UVM-based verification environments.
• Develop and verify real-number models (RNM) for analog blocks.
• Verify interactions between analog and digital components.
• Perform functional coverage analysis, debug failures, and drive coverage closure.
• Collaborate with analog design, digital design, and SoC verification teams.
• Manage verification schedules, technical deliverables, and team coordination.
• Support regression execution and verification sign-off.

Required Skills

• Strong experience in Analog/Mixed-Signal (AMS) verification.
• Hands-on expertise in SystemVerilog and UVM.
• Experience with Real Number Modeling (RNM) and mixed-signal verification methodologies.
• Knowledge of analog blocks such as ADCs, DACs, PLLs, oscillators, LDOs, and other mixed-signal IPs.
• Experience with functional coverage, debugging, and regression management.
• Familiarity with AMS simulation tools and verification flows.

Preferred Skills

• Experience with Cadence Virtuoso/AMS Designer or other industry-standard AMS verification tools.
• Knowledge of analog behavioral modeling and SystemVerilog-AMS.
• Experience in semiconductor IP and SoC verification.
• Exposure to verification automation using scripting languages such as Python or TCL.