Analog Layout Engineers

Digicomm Semiconductor; Bengaluru; On-site; INR 900,000 - 1,800,000; Full time

Job summary

Digicomm Semiconductor Private Limited in Bengaluru is seeking Analog Layout Engineers to advance mixed-signal layouts on FinFET nodes from 16nm to 3nm, contributing to high-performance designs.

You will handle PNR flows, CTS, routing and timing closure, with exposure to blocks like SERDES, PHY, HDMI, PLL, ADC/DAC, LDO and Bandgap. A solid grasp of CMOS/Bi-CMOS/SOI/FinFET and AMS IP integration is required.

Qualifications

• Experience in analog/mixed-signal layout design in FinFET nodes from 16nm to 3nm.
• Proficient in PNR flow, CTS, routing and timing closure.
• Experience in critical blocks like SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, and Bandgap.
• Strong CMOS/Bi-CMOS/SOI/FinFET process understanding.
• AMS IP integration for full-chip designs per guidelines.
• Strong routing congestion and physical verification skills.

Responsibilities

• Design analog/mixed-signal layouts for advanced FinFET processes.
• Execute PNR flow including CTS, routing, and timing closure.
• Work on blocks like SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, and Bandgap.
• Understand CMOS/Bi-CMOS/SOI/FinFET processes.
• Integrate AMS IP in full-chip designs per guidelines.
• Resolve routing congestion and perform physical verification in custom layout.

Skills

Analog layout design

Mixed-signal layout

PNR flow

Timing closure

CMOS/SOI/FinFET knowledge

AMS IP integration

Routing congestion debugging

Physical verification

Problem solving

Education

BTECH/MTECH

Job description

Job Description:

Exciting Opportunity for Analog Layout Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development.

Responsibilities:-

• Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm
• Expertise on complete PNR flow CTS,routing, Timing Closure.
• Hands on experience in any or multiple critical blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.
• Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process
• Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process
• Experience in AMS IP integration in full chip according to the guidelines demanded by the Full Chip needs
• Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout

Qualifications:-

BTECH/MTECH

Experience:-

The Engineers with 2 to 8 years of Experience

Requirements: