Analog Layout engineer

ACL Digital; Bengaluru Urban; On-site; INR 4,500,000 - 7,000,000; Full time

Job summary

ACL Digital in Bangalore is seeking a Senior/Lead AMS IC Layout Engineer to join immediately or on notice. 5–10 years of Analog & Mixed‑Signal IP layout experience and hands‑on in 55nm and 22nm nodes are required.

Own end-to-end IP layout from floorplanning to signoff, collaborating with circuit designers. Proficient in Cadence Virtuoso/Virtuoso XL and Mentor Calibre for DRC/LVS/PEX closure. Preferred IP domains: LDOs, ADCs/DACs, Bandgap references, oscillators, level shifters, POR/monitors.

Qualifications

• 5–10 years of Analog & Mixed-Signal IP development.
• 55nm (Primary) & 22nm (Secondary) nodes.
• Cadence Virtuoso / Virtuoso XL and Mentor Calibre (DRC, LVS, PEX/LPE debug & closure).
• Deep working knowledge of ESD-aware layout, Deep N-Well isolation, Guard Rings, matching-sensitive layouts, and EM/IR drop closure.
• Strong ability to work directly with circuit designers to drive layout verification and signoff.

Responsibilities

• Own end-to-end IP-level layout delivery from floorplanning through signoff.
• Collaborate with circuit designers to drive layout verification and signoff.
• Ensure layout quality for 55nm and 22nm nodes and interfaces.

Skills

AMS IC Layout

IP layout delivery

Layout verification

Collaborative design

Tools

Cadence Virtuoso

Virtuoso XL

Mentor Calibre

DRC/LVS/PEX

Job description

Analog/Mixed-Signal (AMS) IC Layout talent in Bangalore, with an emphasis on immediate joiners and candidates on notice period.

Hiring: Senior / Lead Analog & Mixed-Signal IC Layout Engineer

Location: Bengaluru, India ??

Experience: 5 – 10 Years

Notice Period: Immediate Joiners / Serving Notice Period Preferred

Are you an AMS IC Layout Engineer with strong hands-on experience in 55nm & 22nm nodes? We are looking for an experienced engineer to own end-to-end IP-level layout delivery from floorplanning through signoff!

Key Responsibilities & Skills Required:

• Experience: 5–10 years in Analog & Mixed-Signal IP development.
• Nodes: Extensive experience in 55nm (Primary) & 22nm (Secondary) nodes.
• Tools: Proficient in Cadence Virtuoso / Virtuoso XL and Mentor Calibre (DRC, LVS, PEX/LPE debug & closure).
• Technical Depth: Deep working knowledge of ESD-aware layout, Deep N-Well isolation, Guard Rings, matching-sensitive layouts, and EM/IR drop closure.
• Collaboration: Strong ability to work directly with circuit designers to drive layout verification and signoff.

Preferred IP Domain Background:

Experience working on precision IPs:

• LDOs & Power Management IPs
• ADCs / DACs
• Bandgap & Voltage References
• Oscillators, Comparators & Bias Circuits
• Level Shifters & POR / Voltage Monitors