Analog Layout engineer

ACL Digital; Bengaluru; On-site; INR 2,400,000 - 4,200,000; Full time

Job summary

ACL Digital is seeking a Senior/Lead Analog & Mixed-Signal IC Layout Engineer in Bengaluru. The role focuses on end-to-end IP-level layout delivery from floorplanning through signoff for AMS IPs at 55nm and 22nm nodes.

Immediate joiners or those on notice are preferred. The candidate should have 5–10 years of experience in Analog & Mixed-Signal IP development with deep expertise in ESD-aware layouts, deep N-Well isolation, guard rings, and EM/IR drop closure.

Qualifications

• 5–10 years in Analog & Mixed-Signal IP development.
• Experience with 55nm (primary) and 22nm (secondary) nodes.
• Deep working knowledge of ESD-aware layout, Deep N-Well isolation, guard rings, matching-sensitive layouts.

Responsibilities

• Own end-to-end IP-level layout delivery from floorplanning through signoff.
• Collaborate directly with circuit designers to drive layout verification and signoff.
• Deliver robust layouts with EM/IR drop closure and reliable matching.

Skills

AMS IC Layout

55nm

22nm

IP layout

Floorplanning

Signoff

EM/IR guard rings

ESD-aware layout

Deep N-Well isolation

Collaboration with circuit designers

Job description

Analog/Mixed-Signal (AMS) IC Layout talent in Bangalore, with an emphasis on immediate joiners and candidates on notice period.

Hiring: Senior / Lead Analog & Mixed-Signal IC Layout Engineer

Experience: 5 – 10 Years

Notice Period: Immediate Joiners / Serving Notice Period Preferred

Are you an AMS IC Layout Engineer with strong hands-on experience in 55nm & 22nm nodes? We are looking for an experienced engineer to own end-to-end IP-level layout delivery from floorplanning through signoff!

Key Responsibilities & Skills Required:

• Experience: 5–10 years in Analog & Mixed-Signal IP development.
• Nodes: Extensive experience in 55nm (Primary) & 22nm (Secondary) nodes.
• Technical Depth: Deep working knowledge of ESD-aware layout, Deep N-Well isolation, Guard Rings, matching-sensitive layouts, and EM/IR drop closure.
• Collaboration: Strong ability to work directly with circuit designers to drive layout verification and signoff.

Preferred IP Domain Background:

Experience working on precision IPs:

Level Shifters & POR / Voltage Monitors