Analog layout_4-8 years_Bangalore_Immediate joiner

AIonSi India Pvt Ltd; Bengaluru South; On-site; INR 900,000 - 1,500,000; Full time

Job summary

AIonSi India Pvt Ltd in Bengaluru South is seeking an Analog Layout Engineer to create and optimize analog/mixed-signal layouts for complex IP/SoC blocks. You will collaborate with circuit design and verification teams, perform LVS/DRC checks, and support tape-out activities.

You will contribute to layout methodologies, participate in design reviews, and assist in debugging during verification and sign-off, aligning with project schedules and quality targets.

Qualifications

• Strong hands-on experience in analog and mixed-signal layout design, including transistor-level layout, matching techniques, and parasitic-aware design.
• Proficiency with industry-standard layout and verification tools (Cadence Virtuoso, Calibre) and familiarity with DRC, LVS, and parasitic extraction flows.
• Solid understanding of CMOS processes, physical design constraints, and layout considerations for precision analog, RF, or high-speed interfaces.
• Ability to collaborate closely with circuit design and verification teams, interpret schematics, and translate design intent into robust layouts.
• 4-8 years of professional experience in analog layout or closely related VLSI physical design roles, preferably with complex SoC or IP projects.
• Strong problem-solving, communication, and documentation skills, with the ability to work independently and meet immediate project timelines.
• Exposure to automotive, functional safety, or high-reliability semiconductor environments is an advantage.

Responsibilities

• Create and optimize analog and mixed-signal layout designs.
• Perform LVS and DRC checks to ensure layout compliance.
• Support tape-out activities and sign-off processes.
• Work on complex IP and SoC-level blocks and participate in design reviews.
• Contribute to layout methodologies and best practices.
• Assist in debug and optimization during verification and sign-off, adhering to schedules.

Skills

Analog layout

Mixed-signal layout

Transistor-level layout

CMOS processes

Layout verification tools

LVS/DRC

Parasitic extraction

Collaboration with design teams

4-8 years experience

Electrical engineering basics

Education

Bachelor's or Master's in Electronics or Electrical Engineering

Tools

Cadence Virtuoso

Calibre

Parasitic extraction tools

Job description

Company Description

AIonSi is a semiconductor solutions startup delivering VLSI design and verification, automotive functional safety, and artificial intelligence solutions to semiconductor clients worldwide. Led by a team of seven industry experts, the company focuses on end-to-end ownership of complex SoC designs, from initial concept through final implementation. AIonSi positions itself as a one-stop platform, emphasizing best-in-class service and uncompromising quality. The organization offers deep expertise in IP and SoC design, integration, verification, gate-level simulation (GLS), and physical design, providing a comprehensive environment for engineering professionals to grow their skills.

Role Description

This is a full-time, on-site Analog Layout Engineer role based in Bengaluru South. The individual in this position will be responsible for creating and optimizing analog and mixed-signal layout designs, ensuring compliance with design rules, performance targets, and reliability requirements. Daily tasks include collaborating with circuit design engineers, performing layout vs. schematic (LVS) and design rule checks (DRC), and supporting tape-out activities. The role involves working on complex IP and SoC-level blocks, participating in design reviews, and contributing to layout methodologies and best practices. The engineer will also assist in debug and optimization during verification and sign-off, adhering to project schedules and quality standards.

Qualifications

• Strong hands-on experience in analog and mixed-signal layout design, including transistor-level layout, matching techniques, and parasitic-aware design.
• Proficiency with industry-standard layout and verification tools (such as Cadence Virtuoso, Calibre or equivalent) and familiarity with DRC, LVS, and parasitic extraction flows.
• Solid understanding of CMOS processes, physical design constraints, and layout considerations for precision analog, RF, or high-speed interfaces.
• Ability to collaborate closely with circuit design and verification teams, interpret schematics, and translate design intent into robust layouts.
• Relevant academic background, such as a Bachelor's or Master's degree in Electronics, Electrical Engineering, or a related discipline.
• 4-8 years of professional experience in analog layout or closely related VLSI physical design roles, preferably with complex SoC or IP projects.
• Strong problem-solving, communication, and documentation skills, with the ability to work independently and meet immediate project timelines.
• Exposure to automotive, functional safety, or high-reliability semiconductor environments is an advantage.