AMS Verification Engineer

EaseBiz; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

EaseBiz in Bengaluru, India, seeks a verification engineer specializing in analog and mixed-signal IPs, subsystems, and SoCs. You will apply SystemVerilog, UVM, and MS methodologies to build testbenches, assertions, and coverage infrastructure.

Responsibilities include verification of ADCs/DACs/PLLs and other interfaces, plus rigorous debugging and sign-off on verification results. Prior experience with Verilog-AMS and RNM is advantageous.

Qualifications

• Experience with SystemVerilog, UVM and UVM-MS
• Hands-on testbench development and assertion creation
• Strong knowledge of mixed-signal verification methodologies
• Experience with Verilog-AMS and RNM concepts
• Proficiency in coverage analysis and sign-off activities
• Ability to debug and analyze mixed-signal simulations

Responsibilities

• Verify Analog and Mixed-Signal IPs, Subsystems, and SoCs
• Develop testbenches, assertions, and checkers for verification
• Perform coverage analysis and lead verification sign-off
• Conduct mixed-signal simulations including Verilog-AMS and RNM
• Verify ADCs, DACs, PLLs, Op-Amps and other interfaces
• Debug and analyze mixed-signal designs to ensure correctness

Skills

SystemVerilog

UVM

UVM-MS

Testbench development

Assertions

Coverage analysis

Job description

• Verification of Analog and Mixed-Signal IPs, Subsystems, and SoCs
• SystemVerilog, UVM, and UVM-MS methodologies
• Testbench development, assertions, checkers, and functional coverage
• Verilog-AMS, Verilog-A, WREAL, and Real Number Modeling (RNM)
• Mixed-signal simulations, debugging, and analysis
• Verification of ADCs, DACs, PLLs, Op-Amps, and other mixed-signal interfaces
• Coverage analysis and verification sign-off activities