AMS

Ignitarium Inc.; Ernakulam; On-site; INR 1,200,000 - 2,200,000; Full time

Job summary

Neurealm Company in India is seeking an AMS verification engineer to develop and execute verification plans for AMS/analog IPs and mixed-signal SoCs. You will build verification environments using Verilog-AMS, SystemVerilog, and UVM, and collaborate with analog, digital, and validation teams.

The role requires 2+ years of AMS verification experience, knowledge of ADC/DAC, PLL, and high-speed interfaces, and scripting skills in Python/Perl/Shell. Apply now.

Qualifications

• 2+ years of AMS verification experience.
• Strong understanding of analog and mixed-signal concepts.
• Experience with Cadence/Synopsys simulation tools.
• Knowledge of Verilog-AMS, SystemVerilog, UVM, and scripting languages like Python/Perl/Shell.

Responsibilities

• Develop and execute verification plans for AMS/analog IPs and mixed-signal SoCs.
• Build and maintain AMS verification environments using Verilog, Verilog-AMS, SystemVerilog, or UVM.
• Perform functional, behavioral, and mixed-signal simulations.
• Collaborate closely with analog design, digital design, and validation teams.
• Debug simulation failures and identify root causes.
• Create testbenches, assertions, coverage models, and regression suites.
• Support silicon bring-up and post-silicon validation activities when required.

Skills

Verilog-AMS

SystemVerilog

UVM

Python

Perl

Shell scripting

Analog/mixed-signal concepts

Education

Bachelor’s/Master’s degree in Electronics/ECE/VLSI or related field

Tools

Cadence/Synopsys simulation tools

Job description

## AMS03-06-2026 16:21:51Job\\_304324---* Chennai, Tamil Nadu, India (WAC\\_007)* Bangalore, Karnataka, India (WAC\\_003)* Kochi, Kerala, India (WAC\\_004)### Key Responsibilities* Develop and execute verification plans for AMS/analog IPs and mixed-signal SoCs.* Build and maintain AMS verification environments using Verilog, Verilog-AMS, SystemVerilog, or UVM.* Perform functional, behavioral, and mixed-signal simulations.* Collaborate closely with analog design, digital design, and validation teams.* Debug simulation failures and identify root causes.* Create testbenches, assertions, coverage models, and regression suites.* Support silicon bring-up and post-silicon validation activities when required.### Required Skills* Strong understanding of analog and mixed-signal concepts.* Experience with Cadence/Synopsys simulation tools.* Knowledge of Verilog-AMS, SystemVerilog, UVM, and scripting languages like Python/Perl/Shell.* Familiarity with ADC/DAC, PLL, SerDes, PMIC, or high-speed interface verification is preferred.* Good debugging and problem-solving skills.### Qualification* Bachelor’s/Master’s degree in Electronics/ECE/VLSI or related field.* 2+ years of experience in AMS verification preferred.Apply Now