STA Design Engineer

European Tech Recruit; Cork; On-site; EUR 85,000 - 120,000; Full time

Job summary

European Tech Recruit is seeking an experienced Static Timing Analysis (STA) Engineer for a world-leading semiconductor company in Cork, Ireland. You will perform timing signoff, lead timing closure, and develop STA methodologies alongside RTL, Synthesis, and Physical Design teams to optimise performance.

The role focuses on delivering timing solutions for complex ASICs/SoCs, developing automation for timing data, and ensuring designs meet signoff criteria.

Qualifications

• 4+ years of experience in Static Timing Analysis or a closely related field.
• Experience using STA tools for hierarchical timing analysis on large SoCs.
• Hands-on experience with timing ECO tools.
• Strong scripting and automation skills (Python, Tcl, or Perl).
• Understanding of ASIC flow from RTL to GDS.

Responsibilities

• Perform static timing analysis and timing closure for complex cores and full-chip SoCs.
• Develop and improve STA methodologies, flows and timing signoff processes.
• Drive timing accuracy while improving analysis turnaround times.
• Ensure designs meet timing signoff criteria and project quality standards.
• Develop automation for timing and power data collection, processing and analysis.
• Support project planning by contributing to technical milestones and deliverables.
• Deliver project objectives on schedule while providing production support.
• Troubleshoot and resolve timing-related issues throughout the development lifecycle.

Skills

Static timing analysis

PrimeTime

Python scripting

RTL to GDS flow

Cross-functional collaboration

Tools

PrimeTime

PrimeShield

Tempus

Tweaker

PrimeClosure

PTECO

Tempus ECO

Job description

We are looking for an experienced Static Timing Analysis (STA) Engineer to join a world-leading semiconductor company developing next-generation, high-performance, low-power SoCs. You'll play a key role in timing signoff, timing closure and methodology development, working closely with cross-functional engineering teams to deliver cutting-edge silicon.

As an STA Engineer, you will be responsible for performing static timing analysis, developing and validating timing constraints, and driving timing closure across complex ASICs and SoCs. Working with RTL, Synthesis and Physical Design teams, you'll help optimise performance, power and area while ensuring designs meet timing signoff requirements.

Responsibilities

• Perform static timing analysis and timing closure for complex cores and full-chip SoCs.
• Develop and improve STA methodologies, flows and timing signoff processes.
• Drive timing accuracy while improving static and dynamic analysis turnaround times.
• Ensure designs meet timing signoff criteria and project quality standards.
• Develop automation for timing and power data collection, processing and analysis.
• Support project planning by contributing to technical milestones and deliverables.
• Deliver project objectives on schedule while providing production support when required.
• Troubleshoot and resolve timing-related issues throughout the development lifecycle.

Requirements

• Experience using STA tools such as PrimeTime, PrimeShield or Tempus for hierarchical timing analysis on large SoCs.
• Hands-on experience with timing ECO tools including Tweaker, PrimeClosure, PTECO or Tempus ECO.
• Strong scripting and automation skills using Python, Tcl and/or Perl.
• Solid understanding of the ASIC implementation flow from RTL through to GDS.
• Knowledge of Design for Parametric Yield would be beneficial.
• Experience with extraction and circuit simulation tools is advantageous.
• Strong analytical and problem-solving skills with a practical, results-focused approach.
• Excellent communication skills and the ability to collaborate effectively within multidisciplinary engineering teams.
• 4+ years' experience in Static Timing Analysis or a closely related field.

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