Physical Design Implementation

European Tech Recruit; Cork; On-site; EUR 90,000 - 120,000; Full time

Job summary

European Tech Recruit seeks a Senior Physical Design Implementation Engineer for a global semiconductor leader in Ireland. You will drive hands-on PD across the full lifecycle from netlist handoff to GDS, with emphasis on floorplanning, power planning, placement, CTS and routing.

The ideal candidate has 4+ years in PD, strong experience with 10nm or smaller nodes, timing-closure strategies, power integrity, and PD verification to ensure DRC-clean layouts.

Qualifications

• 4+ years hands-onPhysical Design experience.
• Experience from netlist handoff to GDS with floorplanning, power, placement, CTS and routing.
• Strong background with 10nm and below node flows for implementation and signoff.

Skills

Years of PD experience

PD lifecycle mastery

Advanced-node PD tools

STA/timing-closure

Power integrity analysis

Physical Verification flows

Tools

Cadence

Synopsys

GDS tooling

Job description

Senior Physical Design Implementation Engineer

Would you like to work for one of the global semiconductor leaders? Now hiring for a Senior Physical Design Implementation Engineer to join the team.

Key experience needed for the Senior Physical Design Implementation Engineer role:

• 4+ years of hands-on experience working in Physical Design.
• Strong grasp of the full PD lifecycle, from netlist handoff through GDS, including floorplanning, power planning, placement, CTS, routing, and associated optimization.
• Solid background using advanced-node physical design tools (10nm and below) for implementation and signoff.
• Deep understanding of STA concepts, timing-closure strategies, and how timing impacts congestion, routing quality, and power.
• Familiarity with power analysis and power-integrity evaluation techniques.
• Working knowledge of Physical Verification flows and achieving DRC-clean layouts.

Keywords: ASIC / Physical Design / SoC / RTL / GDS / Place & Route / STA / RTL-to-GDS / IP Design / Digital Design / Cadence / Synopsys / Semiconductor / Timing Closure / PPA Optimization

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