Senior STA Engineer - SoC Timing Signoff and Automation

European Tech Recruit; Cork; On-site; EUR 85,000 - 120,000; Full time

Job summary

European Tech Recruit is seeking an experienced Static Timing Analysis (STA) Engineer for a world-leading semiconductor company in Cork, Ireland. You will perform timing signoff, lead timing closure, and develop STA methodologies alongside RTL, Synthesis, and Physical Design teams to optimise performance.

The role focuses on delivering timing solutions for complex ASICs/SoCs, developing automation for timing data, and ensuring designs meet signoff criteria.

Qualifications

• 4+ years of experience in Static Timing Analysis or a closely related field.
• Experience using STA tools for hierarchical timing analysis on large SoCs.
• Hands-on experience with timing ECO tools.
• Strong scripting and automation skills (Python, Tcl, or Perl).
• Understanding of ASIC flow from RTL to GDS.

Responsibilities

• Perform static timing analysis and timing closure for complex cores and full-chip SoCs.
• Develop and improve STA methodologies, flows and timing signoff processes.
• Drive timing accuracy while improving analysis turnaround times.
• Ensure designs meet timing signoff criteria and project quality standards.
• Develop automation for timing and power data collection, processing and analysis.
• Support project planning by contributing to technical milestones and deliverables.
• Deliver project objectives on schedule while providing production support.
• Troubleshoot and resolve timing-related issues throughout the development lifecycle.

Skills

Static timing analysis

PrimeTime

Python scripting

RTL to GDS flow

Cross-functional collaboration

Tools

PrimeTime

PrimeShield

Tempus

Tweaker

PrimeClosure

PTECO

Tempus ECO

Job description

European Tech Recruit is seeking an experienced Static Timing Analysis (STA) Engineer for a world-leading semiconductor company in Cork, Ireland. You will perform timing signoff, lead timing closure, and develop STA methodologies alongside RTL, Synthesis, and Physical Design teams to optimise performance.

The role focuses on delivering timing solutions for complex ASICs/SoCs, developing automation for timing data, and ensuring designs meet signoff criteria.