Static Timing Analysis Engineer - (Graphics / STA / Semiconductors) - Visas Supported

European Tech Recruit; Cork; On-site; EUR 70,000 - 110,000; Full time

Job summary

The GPU STA Team in Cork, Ireland is seeking an experienced GPU Engineer to strengthen timing and power-aware GPU design. You will join a global semiconductor leader focused on high-performance GPUs and low-power architectures.

You will enhance block- and top-level timing, develop sign-off methodologies, and push for faster, more power-efficient graphics solutions while collaborating across multi-disciplinary teams.

Qualifications

• Master’s or Bachelor's degree in Computer Engineering or Electrical Engineering.
• 3+ years of industrial work experience.
• Expertise in timing analysis for large SoCs and GPUs.
• Hands-on experience with Primetime, Primeshield, Tempus and Redhawk SC.

Responsibilities

• Develop chip signoff methodologies and timing flows for low-power GPUs.
• Enhance STA and PDN/Timing for design closure under low-power architectures.
• Drive timing accuracy and reduce turn-around time in flows.
• Create automation for timing and power data mining and processing.
• Contribute to project proposals with milestones and deliverables.
• Deliver project goals with production support and resolve issues.

Skills

Python

TCL

Perl

Timing analysis

GPU timing

Education

Master’s/Bachelors in Computer/Electrical Engineering

Tools

Primetime

Primeshield

Tempus

Redhawk SC

PTECO

Tweaker

Job description

A fantastic opportunity for an experienced GPU Engineer to join a leading Global Semiconductor Company, working alongside their GPU STA Team in Cork, Ireland.

You will work alongside a team responsible for evaluating block-level and top-level timing to ensure optimal performance and power efficiency in advanced GPUs. Your role will be crucial in developing high-performance, low-power graphics solutions that drive the future of technology.

Responsibilities:

You will be member of team developing chip signoff methodology and flow:

• Enhancing STA and PDN / Timing technologies for design closure methodology with unique challenges driven by Low power architecture, Si Variation, Low voltage operation and other challenges.
• Driving accuracy of timing closure and static/dynamic flows to reduce turn around time
• Automation for timing and power data mining and processing
• Participating in project proposal development including key milestones and deliverables
• Executing and deliver project goals in a timely manner with production support
• Resolving issues in all phases of development to assure smooth project execution

Good to have:

• Master’s/Bachelors of Computer Engineering or Electrical Engineering
• 3+ years industrial work experience.
• Expertise in Primetime, Primeshield and Tempus based, hierarchical analysis for large SoCs
• Expertise in Redhawk SC for flow development of static/dynamic/DVD
• Hands on Tweaker, Tempus ECO and PTECO for timing closure
• Highly Proficient in Python, TCL and Perl
• Excellent problem-solving skills and results-driven, able to work and drive practical solutions under research environment.
• Good communication skill and personal skills in a multi-disciplinary, fast-paced engineering environment

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