Staff Physical Design Engineer

European Tech Recruit; Cork; On-site; EUR 90,000 - 130,000; Full time

Job summary

European Tech Recruit is partnering with a semiconductor technology organisation to recruit a Senior/Staff Physical Design Engineer. The role focuses on physical implementation, PPA optimisation, STA, TCL, and Perl scripting across 10nm and below technology nodes.

You will drive floorplanning, CTS, routing, power planning and timing closure while collaborating with cross-functional teams to push performance, power, and area targets within a fast-paced R&D environment.

Qualifications

• 4+ years of experience in physical design.
• Experience from netlist to GDS flow.
• Proficient in STA and timing closure.
• Automation skills with Perl and TCL.
• Strong cross-functional communication.

Responsibilities

• Execute physical implementation from floorplanning to GDS.
• Develop automation scripts to improve design flows.
• Drive timing closure and power optimisation.
• Collaborate with cross-functional teams to meet PPA targets.
• Analyse design data to identify optimization opportunities.
• Stay updated on industry trends in physical design.
• Ensure compliance with design rules and PPA requirements.

Skills

Physical design

Timing closure

Power integrity

Automation scripting

Cross-functional collaboration

Communication skills

Tools

Perl

TCL

GDSII

Floorplanning tools

Job description

Senior/Staff Physical Design Engineer – Physical Implementation / PPA Optimisation / STA / TCL / Perl

We are currently partnered with a semiconductor technology organisation developing complex, high-speed designs with demanding performance, power and area (PPA) targets. This opportunity focuses on physical design implementation from floorplanning through to GDS, timing closure, power optimisation and the development of innovative methodologies and automation flows for advanced technology nodes.

Key responsibilities

• Execute physical implementation for complex, high-speed designs from floorplanning through to GDS.
• Research and develop innovative physical design methodologies to improve PPA and push implementation limits.
• Develop scripts and flows to automate and enhance physical design processes.
• Collaborate with cross-functional teams to understand design requirements and address physical implementation challenges.
• Drive timing closure and power optimisation while considering congestion, routing and overall design performance.
• Research industry trends and innovations in physical design to align methodologies and deliverables with best practices.
• Analyse implementation data and benchmarks to identify issues, trends and opportunities for improvement.
• Work across teams to identify and deliver PPA improvements while ensuring design quality and compatibility with required standards.

Key requirements

• At least 4 years of relevant experience in physical design.
• Knowledge of the complete physical design flow from netlist to GDS, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing and associated optimisation steps.
• Experience with physical design implementation tools for advanced technology nodes of 10nm and below.
• Strong understanding of static timing analysis (STA) and timing closure methodologies, including their impact on congestion, routing and power.
• Understanding of power analysis and power integrity analysis.
• Knowledge of physical verification and design rule check (DRC) closure.
• Advanced automation skills using Perl and TCL, including developing and supporting physical design flows.
• Strong communication skills and the ability to work effectively in cross-functional engineering teams.

Keywords

Senior Physical Design Engineer / Staff Physical Design Engineer / Physical Design / Physical Implementation / Semiconductor Design / VLSI / ASIC Design / Netlist to GDS / GDSII / Floorplanning / Power Planning / Placement / Clock Tree Synthesis / CTS / Routing / Physical Design Flow / PPA Optimisation / Power Performance Area / Timing Closure / Static Timing Analysis / STA / Timing Analysis / Congestion Analysis / Routing Optimisation / Power Optimisation / Power Analysis / Power Integrity Analysis / Physical Verification / Design Rule Check / DRC Closure / Advanced Technology Nodes / 10nm / Sub-10nm Process Technology / Physical Design Automation / TCL / Perl / Scripting / Flow Development / Flow Optimisation / High-Speed Designs / Complex Designs / Benchmark Analysis / Cross-Functional Engineering / Semiconductor Engineering

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