Senior RTL Digital Designer (SystemVerilog) – Onsite Cork

Software Placements; Cork; On-site; EUR 111,000 - 166,000; Full time

Job summary

Software Placements in Cork City, Ireland, seeks a Contract Front-End Digital Design Engineer for a 6-month daily rate engagement. Onsite 5 days a week, you will translate specifications into synthesizable RTL, develop with SystemVerilog/Verilog, and work across global teams to meet milestones.

The role focuses on release management, QA checks, and collaboration with design, verification, and program teams to deliver high-quality IP releases.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related discipline.
• 2–5 years of experience in digital logic design, RTL development, and Verilog/SystemVerilog.
• Experience with RTL simulation, timing analysis, and industry-standard EDA tools.

Responsibilities

• Translate architectural and microarchitectural specifications into robust, synthesizable RTL.
• Develop and maintain digital designs using SystemVerilog/Verilog.
• Design and implement modules including control logic, datapaths, state machines, interfaces, and complex digital blocks.
• Perform RTL design, simulation, linting, synthesis, and timing analysis.
• Work with verification teams to develop design specifications, test plans, and functional coverage requirements.
• Debug RTL and simulation issues and resolve functional, performance, and design-quality problems.
• Analyse synthesis results and optimise designs for power, performance, and area (PPA).
• Collaborate with physical design teams to address timing, area, and implementation-related issues.
• Participate in design reviews and contribute to coding standards, methodologies, and best practices.
• Support design bring-up and silicon debug where required.
• Contribute to improving design flows, automation, and development methodologies.

Skills

RTL design

SystemVerilog

Verilog

Debugging

Education

Electrical Engineering / Electronics Engineering / Computer Engineering

Tools

Python scripting

ClearCase

Synopsys Design Compiler/PrimeTime

RTL simulators

Job description

Software Placements in Cork City, Ireland, seeks a Contract Front-End Digital Design Engineer for a 6-month daily rate engagement. Onsite 5 days a week, you will translate specifications into synthesizable RTL, develop with SystemVerilog/Verilog, and work across global teams to meet milestones.

The role focuses on release management, QA checks, and collaboration with design, verification, and program teams to deliver high-quality IP releases.