Senior Digital Designer

Software Placements; Cork; On-site; EUR 111,000 - 166,000; Full time

Job summary

Software Placements in Cork City, Ireland, seeks a Contract Front-End Digital Design Engineer for a 6-month daily rate engagement. Onsite 5 days a week, you will translate specifications into synthesizable RTL, develop with SystemVerilog/Verilog, and work across global teams to meet milestones.

The role focuses on release management, QA checks, and collaboration with design, verification, and program teams to deliver high-quality IP releases.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related discipline.
• 2–5 years of experience in digital logic design, RTL development, and Verilog/SystemVerilog.
• Experience with RTL simulation, timing analysis, and industry-standard EDA tools.

Responsibilities

• Translate architectural and microarchitectural specifications into robust, synthesizable RTL.
• Develop and maintain digital designs using SystemVerilog/Verilog.
• Design and implement modules including control logic, datapaths, state machines, interfaces, and complex digital blocks.
• Perform RTL design, simulation, linting, synthesis, and timing analysis.
• Work with verification teams to develop design specifications, test plans, and functional coverage requirements.
• Debug RTL and simulation issues and resolve functional, performance, and design-quality problems.
• Analyse synthesis results and optimise designs for power, performance, and area (PPA).
• Collaborate with physical design teams to address timing, area, and implementation-related issues.
• Participate in design reviews and contribute to coding standards, methodologies, and best practices.
• Support design bring-up and silicon debug where required.
• Contribute to improving design flows, automation, and development methodologies.

Skills

RTL design

SystemVerilog

Verilog

Debugging

Education

Electrical Engineering / Electronics Engineering / Computer Engineering

Tools

Python scripting

ClearCase

Synopsys Design Compiler/PrimeTime

RTL simulators

Job description

Our client a leading Multinational Semiconductor Telecom requires Contract Front-End Digital Design Engineer for 6 month daily rate position based in Cork City, Ireland.

You will be required to be onsite 5 days per week.

Role:

Support Foundation IP development and release activities through RTL Verilog updates, quality assurance, and release management.

Responsibilities include implementing and validating RTL design changes, managing ClearCase-based release processes, performing QA checks for Foundation IP deliverables, and enhancing release workflows through Python scripting and automation.

The role requires close collaboration across multiple global sites and cross-functional teams, with a strong focus on daily communication, coordination, and proactive issue resolution to ensure project milestones and release deadlines are met. The successful candidate will work with design, verification, integration, and program teams to deliver high-quality IP releases, improve process efficiency, and maintain configuration management and release documentation

Responsibilities:

• Translate architectural and microarchitectural specifications into robust, synthesizable RTL.
• Develop and maintain digital designs using SystemVerilog/Verilog.
• Design and implement modules including control logic, datapaths, state machines, interfaces, and complex digital blocks.
• Perform RTL design, simulation, linting, synthesis, and timing analysis.
• Work with verification teams to develop design specifications, test plans, and functional coverage requirements.
• Debug RTL and simulation issues and resolve functional, performance, and design-quality problems.
• Analyse synthesis results and optimise designs for power, performance, and area (PPA).
• Collaborate with physical design teams to address timing, area, and implementation-related issues.
• Participate in design reviews and contribute to coding standards, methodologies, and best practices.
• Support design bring-up and silicon debug where required.
• Contribute to improving design flows, automation, and development methodologies.

Education:

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.

Experience:

A minimum of 2 - 5 years experience in the following:

• Strong knowledge of digital logic design and RTL development.
• Proficiency in Verilog/SystemVerilog.
• Experience with RTL simulation and debugging using industry-standard EDA tools.
• Understanding of synthesis, static timing analysis, clocking, resets, and design constraints.
• Familiarity with ASIC design flows from RTL through synthesis and implementation.
• Strong problem-solving and analytical skills.
• Good communication and teamwork skills.

Nice to have:

• Experience with UVM, SystemVerilog Assertions (SVA), or formal verification.
• Knowledge of AMBA protocols, such as AXI, AHB, or APB.
• Experience with low-power design techniques and methodologies.
• Familiarity with CDC/RDC analysis.
• Experience with synthesis and timing tools such as Synopsys Design Compiler/PrimeTime or equivalent.
• Experience with scripting languages such as Python, Perl, or Tcl.
• Understanding of physical design concepts and RTL-to-GDSII flows.
• Experience with high-speed interfaces, CPUs, accelerators, memory subsystems, or other complex SoC components.

Contact:

For further information please contact Mícheál at Software Placements Ltd on 00353 1 5254642 or email [e-mail]