Onsite Cork Front-End Digital Design Engineer (RTL/SV)

Software Placements; Cork; On-site; EUR 65,000 - 111,000; Full time

Job summary

Software Placements in Cork, Ireland, seeks an embedded-frontier Digital Design Engineer for a 6‑month on-site contract. You will support Foundation IP development, RTL updates and release management across global teams, delivering high‑quality IP releases on schedule.

You will design in SystemVerilog/Verilog, perform RTL synthesis and timing analyses, and collaborate with verification and physical design to optimise PPA while maintaining robust release documentation.

Qualifications

• Bachelor's or Master's degree in Electrical, Electronics or Computer Engineering.
• 2+ years in digital IC/ASIC/SoC design with RTL/Verilog know‑how.
• Proficient in Verilog/SystemVerilog and RTL simulation/debugging.
• Familiar with ASIC design flows, synthesis, STA, clocks and constraints.
• Experience with Python scripting and automation is a plus.

Responsibilities

• Translate specs into robust, synthesizable RTL.
• Develop digital designs using SystemVerilog/Verilog.
• Implement modules with control logic, datapaths and state machines.
• Perform RTL design, simulation, linting, synthesis and timing analysis.
• Work with verification to define tests and coverage.
• Debug RTL and timing issues; resolve performance and quality problems.
• Analyse synthesis results to optimize power, performance and area.
• Collaborate with physical design to address timing and area.
• Participate in design reviews and improve coding standards.
• Support bring-up and silicon debug as required.
• Contribute to improved design flows and automation.

Skills

RTL design

SystemVerilog/Verilog

AMBA protocols

Python scripting

Synthesis & timing

Education

Bachelor's or Master's in Electrical/Electronics/Computer Eng

Tools

Synopsys Design Compiler

Synopsys PrimeTime

ClearCase

Job description

Software Placements in Cork, Ireland, seeks an embedded-frontier Digital Design Engineer for a 6‑month on-site contract. You will support Foundation IP development, RTL updates and release management across global teams, delivering high‑quality IP releases on schedule.

You will design in SystemVerilog/Verilog, perform RTL synthesis and timing analyses, and collaborate with verification and physical design to optimise PPA while maintaining robust release documentation.