Senior Design Verification Engineer

Software Placements; Cork; On-site; EUR 77,000 - 125,000; Full time

Job summary

Software Placements is seeking a Contract Digital Design Verification Engineer in Cork City, Ireland. The role involves working on embedded verification across SoC components, with emphasis on UVM-based methodologies, testbench development, and cross-functional collaboration.

The ideal candidate has 3+ years in ASIC verification, familiarity with ARM/RISC-V ISA, and experience with formal verification tools. Onsite 5 days a week; remote options may be considered for the right candidate.

Qualifications

• 3+ years of ASIC design verification experience, preferably with UVM-based.
• Familiarity with ARM or RISC-V ISA verification.
• Experience using formal verification tools like Jasper or VC_Formal is a plus.
• Understanding of processor/microcontroller sub-systems is advantageous.
• Familiarity with AMBA bus protocols is desirable.
• Power-aware verification knowledge is beneficial.
• SystemVerilog assertions familiarity is useful.
• RTL simulation tools experience.
• Scripting with Perl/Python.

Responsibilities

• Develop testbenches and verification components, including UVCs and C models.
• Apply verification methodologies such as UVM and Formal Verification.
• Perform coverage analysis and address gaps with design teams.
• Collaborate with design, SoC and validation groups to resolve issues.
• Support integration into higher-level subsystems and test planning.

Skills

UVM

SystemVerilog

C/C++

Python scripting

Perl

ISA verification

Formal Verification

Testbench development

UVCs

Debugging

Power-aware verification

Coverage-driven verification

AMBA

RTL simulation tools

SystemVerilog assertions

Education

Bachelor's degree in engineering or related field

Tools

Jasper

VC_Formal

Job description

Our client a leading Multinational Semiconductor Company Contract Digital Design Verification Engineer for 6 months daily rate role based in Cork City, Ireland.

100% remote maybe considered for the right candidate.

You will be required to be onsite 5 days per week.

Role:

The Microcontroller Sub-System IP team plays a crucial role in enabling embedded processing solutions across various functions and products.

This team deals with security, power management, and other system-on-chip (SoC) functions across multiple business units (IoT, Mobile, Auto, XR, Compute, etc.).

Responsibilities:

• As a Microcontroller Sub-System Verification Engineer, you’ll play a vital role in advancing technology and growing alongside our dynamic team. Your responsibilities will include:
• Technological Advancements: Be an integral part of our team’s journey toward technological excellence.
• Verification Methodologies: Deploy industry-leading verification methodologies such as Universal Verification Methodology (UVM) and Formal Verification.
• Testbench and Verification Component Development: Create testbenches and verification components, including Universal Verification Components (UVCs), C models, and reusable vertical/horizontal verification environments.
• Coverage Analysis: Ensure comprehensive coverage and collaborate with design teams to address any coverage gaps.
• Cross-Functional Collaboration: Work closely with design, SoC, and validation teams to solve problems at various levels.
• System solutions Support: Assist in integrating design into higher-level subsystems, including test planning, test vector delivery, and test vector debugging.
• Ideally, we’re seeking candidates with the following:
• Positive Attitude: Bring a fun-loving attitude and a passion for inclusive problem-solving.

Education:

• Bachelor’s degree in science, Engineering, or a related field.

Experience:

• 3+ years of ASIC design verification experience, preferably with UVM-based.
• ISA Verification: Familiarity with ARM or RISC-V ISA verification.
• Formal Verification Tools: Experience using formal verification tools like Jasper or VC_Formal is a plus.
• Microcontroller/Sub-System Knowledge: Understanding of processor/microcontroller sub-systems is advantageous.
• AMBA Bus Protocols: Familiarity with AMBA bus protocols is desirable.
• Gate-Level Simulation and Power Extraction: Experience with gate-level simulation debug and power extraction tools is beneficial.
• Power-Aware Verification: Knowledge of power-aware verification methodologies.
• Coverage-Driven Verification: Proficiency in constrained-random verification environments and coverage-driven methodologies.
• System Verilog Assertions: Familiarity with System Verilog assertions.
• Debugging Skills: Ability to debug test failures and report verification results to achieve expected code/functional/line coverage goals.
• RTL Simulation Tools: Extensive usage of RTL simulation tools.
• Scripting Proficiency: Skills in UVM, System Verilog, and Perl/Python shell scripting.
• C/C++ Familiarity: Basic familiarity with C/C++.