Application Specific Integrated Circuit Design Engineer

Brightwater Recruitment; Cork; Hybrid; EUR 101,000 - 129,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

Brightwater Recruitment's Cork-based client is seeking an experienced RTL Design & IP Release Engineer to support the development, integration, QA and release of foundational semiconductor IP. The role combines RTL design and integration with verification, configuration management and IP release activities across global teams to ensure high-quality IP releases on schedule.

The role also involves improving release processes through scripting and automation, collaborating with RTL design,

Qualifications

• Candidate must have strong experience in RTL design and/or RTL integration within an ASIC/semiconductor environment.
• Solid knowledge of Verilog and SystemVerilog.
• Experience with ASIC design and IP integration.
• Understanding of Clock Domain Crossing concepts.
• Experience with IP release flows and configuration management.

Responsibilities

• Implement and validate RTL design and integration changes.
• Support development and release of foundational IP.
• Perform QA checks on RTL and IP deliverables.
• Carry out CDC and lint analysis and assist with issue resolution.
• Work with configuration and release management to ensure controlled IP releases.
• Develop scripts and automation to improve release workflows.
• Collaborate with RTL design, verification and programme teams across multiple locations.

Skills

RTL design

RTL integration

Verilog/SystemVerilog

ASIC design

IP release

scripting & automation

Python

Configuration management

Release processes

CDC concepts

RTL linting

AMBA protocols

Linux

Tools

Python

Linux

Job description

6 Month Daily Rate Contract / Hybrid / Cork

About the Company

Our client is a leading international company with offices in Cork.

About the Position

We are seeking an experienced RTL Design & IP Release Engineer to support the development, integration, quality assurance and release of foundational semiconductor IP.

This is a hands-on role combining RTL design and integration, verification, configuration management and IP release activities. You will work closely with design, verification, integration and programme teams across multiple global locations to ensure high-quality IP deliverables are released on schedule.

The role will also involve improving existing release processes through scripting and automation, providing an opportunity to make a tangible impact on engineering efficiency and workflow.

Key Responsibilities

• Implement and validate RTL design and integration changes.
• Support the development and release of foundational IP.
• Perform quality assurance checks on RTL and IP deliverables.
• Carry out CDC and lint analysis and support the resolution of identified issues.
• Work with configuration and release management processes to ensure accurate and controlled IP releases.
• Manage and maintain release documentation and associated configuration information.
• Collaborate closely with RTL design, verification, integration and programme teams.
• Coordinate with engineering teams across multiple international locations.
• Identify and proactively resolve issues that could impact project milestones or release deadlines.
• Develop and enhance scripts and automation to improve release workflows and engineering processes.
• Contribute to continuous improvement of IP development and release methodologies.
• Candidate Profile:Strong experience in RTL design and/or RTL integration within an ASIC/semiconductor environment.
• Strong knowledge of Verilog / SystemVerilog.
• Experience with ASIC design and IP integration.
• Understanding of Clock Domain Crossing (CDC) concepts and analysis.
• Experience with RTL linting and quality checks.
• Knowledge of AMBA protocols.
• Experience with scripting and automation.
• Experience working within structured configuration management and release processes.
• Strong communication and coordination skills, particularly within globally distributed engineering teams.
• Experience with IP release flows and semiconductor IP lifecycle management.
• Knowledge or experience of physical verification.
• Python scripting skills.
• Familiarity with source/configuration management tools used within large-scale semiconductor development environments.

Key technologies:

Verilog, SystemVerilog, RTL, ASIC, CDC, Lint, AMBA, Linux, scripting, Python, IP release and configuration management.

Remuneration Package

The daily rate is negotiable.

Contact

Please contact Derek Smyth on 01 5927861 or email.